Chapter five part 6 exceptions
This presentation is the property of its rightful owner.
Sponsored Links
1 / 16

Chapter Five Part 6: Exceptions PowerPoint PPT Presentation


  • 90 Views
  • Uploaded on
  • Presentation posted in: General

Chapter Five Part 6: Exceptions. Exceptions. Hardest part of processor design: hard to get right, hard to make fast. Exceptions: an unexpected event from within the processor. Example: arithmetic overflow.

Download Presentation

Chapter Five Part 6: Exceptions

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Chapter five part 6 exceptions

Chapter FivePart 6: Exceptions


Exceptions

Exceptions

  • Hardest part of processor design: hard to get right, hard to make fast.

  • Exceptions: an unexpected event from within the processor.

  • Example: arithmetic overflow.

  • Interrupt: an event that causes an unexpected change in control flow, comes from outside of the processor.

  • Example: I/O device interrupt

  • Some architectures do not distinguish between these two.

  • MIPS:

    • Exception: any unexpected change in control flow (both internal and external)

    • Interrupt: an unexpected change in control flow that is caused by an external event.


Exceptions1

Exceptions

  • Examples:

  • This chapter: control implementation for

    • Undefined instruction

    • Arithmetic overflow

  • Exceptions often on the critical timing path of a machine.


Exceptions2

Exceptions

  • Actions:

    • Save the address of the offending instruction in the exception program counter (EPC)

    • Transfer control to the OS at some specific address

    • After OS handles error

      • terminate program or

      • continue execution (using EPC)


Exceptions3

Exceptions

  • OS must also know reason for exception. Two methods:

    • Use a status register (called the cause register in MIPS).

      • Holds a field to indicate reason.

      • A single entry point for all exceptions

      • OS decodes the status register to find the cause

    • Vectored Interrupts.

      • The address to which control is transferred is determined by the cause of the exception.


Exceptions4

Exceptions

  • MIPS (uses status register). Need 2 new registers:

    • EPC. 32-bit register used to hold the address of the instruction that caused the interrupt

    • Cause. 32-bit register used to record the cause of the exception. Don’t need all bits.

      • Undefined instruction = 0

      • Arithmetic overflow = 1


Exceptions5

Exceptions

  • Need 2 control signals to cause the EPC and Cause registers to be written:

    • EPCWrite

    • CauseWrite

  • Need 1-bit control signal to set the low-order bit of the Cause register

    • (IntCause).


Exceptions6

Exceptions

  • Must write the exception handler address into the PC. Assume this is C0000000

  • PC is fed by 3-way mux. Must change to 4-way. Controlled by

    • PCSourceS

    • 4th source hardwired to C0000000.


Exceptions7

Exceptions

  • Cannot write PC into EPC (‘cause PC contains PC+4 or instruction following the bad instruction)

    • Use ALU to subtract 4 from PC and write to EPC

    • Already have 4 hardcoded.

    • So connect data write port of EPC to ALU output


Exceptions8

Exceptions


Exceptions9

Exceptions


Exceptions10

Exceptions

  • Control for detecting exceptions

    • Undefined instruction: detected when no next state is defined from state 1 for the op value.

    • Define next state value for all op values not defined as state 10.

    • FSM uses the word other.

    • Arithmetic overflow: Have a signal called overflow from the ALU.

    • Use in FSM to specify an additional possible next state for state 7

  • Real machine: many different exception-causing events.

  • Must include these and still keep control small and fast.


Exceptions11

Exceptions


Exceptions12

Exceptions

  • Some classes of exceptions require that the state in the FSM not change.

  • Discussed in chapter 7.

  • Require us to prevent instruction from changing the machine state.

  • Makes control complex.


Exceptions13

Exceptions

  • Vectored Interrupts. The address to which control is transferred is determined by the cause of the exception.

  • Example. Might define the following:

  • The OS knows the reason for the exception by the address at which it is initiated.

    • Addresses separated by 32 bytes or 8 instructions.

    • OS must record the reason for the exception and either handle the exception or branch in 8 instructions.


The big picture

The Big Picture


  • Login