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Devices and Buses for Device-Networks – Lesson-4: Parallel Communication Buses

Devices and Buses for Device-Networks – Lesson-4: Parallel Communication Buses. 1. IBM Standard Architecture (ISA) Bus and Extended ISA Bus. Two standards for the devices and systems interfacing the PC: 20-bit Address and 16-bit ISA Bus 32-bit Address and 32-bit EISA Bus.

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Devices and Buses for Device-Networks – Lesson-4: Parallel Communication Buses

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  1. Devices and Buses for Device-Networks – Lesson-4: Parallel Communication Buses Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  2. 1. IBM Standard Architecture (ISA) Bus and Extended ISA Bus Two standards for the devices and systems interfacing the PC: • 20-bit Address and 16-bit ISA Bus • 32-bit Address and 32-bit EISA Bus Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  3. ISA and EISA buses - Compatible with IBM PC architecture, • used for connecting devices following IO addresses and interrupt vectors as per IBM PC architecture. Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  4. EISA is 32-bit extension of ISA. • It also supports software interrupt functions and Ethernet devices. Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  5. 2. Peripheral Component Interconnect (PCI) Bus, PCI Extended (PCI/X), Compact PCI (cPCI) Bus Independent from the IBM architecture. Three standards for the devices interfacing with the PC: Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  6. Parallel buses enables a host computer or system to communicate with other devices or systems, for example, to a network interface card (NIC). Number of embedded systems use PCI or PCI/X or cPCI bus when placed in a computer system. Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  7. 64-bit bus, 66 MHz option, 32-bit 33 MHz throughput = 133 MBps, full component level, connector (94-pin connector with 50 signals) and board specifications, multiplexed AD0: 31 bus, dual address 64-bit support, PCI 2.2 [An un-terminated bus, and the signal relay reflected on signal to attain the final value] Refer to Section 3.4 for details Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  8. 133 MBps to as much as 1 GBps Backward compatible with existing PCI cards, used in high bandwidth devices (Fiber Channel, and processors that are part of a cluster and Gigabit Ethernet) PCI-X (PCI extended) Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  9. Maximum 264MBps throughput, uses 8, 16, 32, or 64 bit transfers, 6U cards contain additional pins for user defined I/Os, live insertion support (Hot-Swap), supports two independent buses on the back plane (on different connectors), supports Ethernet, Infiniband, and Star Fabric support (Switched fabric based systems) Compact PCI (cPCI) Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  10. A PCI controller must access one device at a time. all the devices within the host device or system can share the I/O port and memory addresses, cannot share the configuration registers, device cannot modify other configuration registers but can access other device resources or share the work or assist the other device. Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  11. If there are reasons for doing it so, a PCI driver can change the default boot up assignments on configuration transactions. Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  12. A device can initialize at booting time, avoid any address collision, device on boot up disables its interrupt and closes its door to its address space except to the configuration registers space, Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  13. PCI BIOS with the device performs the configuration transactions and then, memory and address spaces automatically map to the address space in the device hosting system Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  14. 3. Advanced Parallel High Speed Buses Refer Section 3.4.3 Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  15. Summary Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  16. We learnt: An I/O card device parallel bus interconnects to a PC or embedded system using ISA or PCI bus Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  17. We learnt • Advanced Parallel High Speed Devices and buses for sophisticated embedded systems have been developed Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

  18. End of Lesson 4 of Chapter 3 Chapter-3 L4: "Embedded Systems - Architecture, Programming and Design" , Raj Kamal, Publs.: McGraw-Hill, Inc.

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