A reconfigurable 1gb stacked sdram board
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A Reconfigurable 1GB Stacked SDRAM Board. Robert F. Hodson - [email protected] Mark Jones, Tak Ng NASA LaRC Darren Boyd. GIFTS. G eosynchronous I maging F ourier T ransform S pectrometer. Data to Naval Centers/ Fleet Demo. Data to NOAA Centers. Australian Ground Station

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A Reconfigurable 1GB Stacked SDRAM Board

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A reconfigurable 1gb stacked sdram board

A Reconfigurable 1GB Stacked SDRAM Board

Robert F. Hodson - [email protected]

Mark Jones, Tak Ng NASA LaRC

Darren Boyd


Gifts

GIFTS

Geosynchronous

Imaging

Fourier

Transform

Spectrometer

2


Gifts mission

Data to Naval

Centers/

Fleet Demo

Data to NOAA

Centers

Australian

Ground Station

& Data Processing

Center

Conus “2”

Conus “1”

Indian Ocean

GIFTS Mission

7 year mission (2 years US, 5 year Indian Ocean)

3


Gifts modules

GIFTS Modules

Modulators

Control Module

Sensor

Module

4


Geo environment

GEO Environment

  • Designed for radiation effects:

    • Total Incident Dose TID 100 krad(Si)

    • Latch-up Immune

    • SEU tolerant

5


Control module

IC

(Instrument Controller) BAE 750

EDS

IO

DL

MEM

I,V,T

Measurement

S/C I/F

SM I/F

Compression

Packetization

1GB

SDRAM

DSP

BAE 750

Control Module

6U CPCI

33MHz, 32 Bit, 3.3 Volt

Fully Redundant

6


Cm architecture

CM Architecture

SM Data I/F

Synchronous Serialized LVDS 21-bit data,16 MHz

MEM

IC

33 MHz/32 bit CPCI Bus

SM Command I/F

422 Differential

X-Band

80 Mbps

IO

DSP

DLINK

SMQ-11

Spacecraft I/F

1553

7


Cm dataflow

CM Dataflow

SM Data I/F

Synchronous Serialized LVDS 21-bit data,16 MHz

MEM

IC

SM Command I/F

422 Differential

X-Band

80 Mbps

IO

DSP

DLINK

SMQ-11

Spacecraft I/F

1553

Requires Sequential “Block” Readout to Downlink

8


Cm dataflow1

CM Dataflow

SM Data I/F

Synchronous Serialized LVDS 21-bit data,16 MHz

MEM

IC

SM Command I/F

422 Differential

X-Band

80 Mbps

IO

DSP

DLINK

SMQ-11

Spacecraft I/F

1553

Requires “Corner-Turned” Readout to DSP

9


Cm dataflow2

CM Dataflow

SM Data I/F

Synchronous Serialized LVDS 21-bit data,16 MHz

MEM

IC

SM Command I/F

422 Differential

X-Band

80 Mbps

IO

DSP

DLINK

SMQ-11

Spacecraft I/F

1553

Diagnostics requires slave capability to IC

10


Memory board design

Memory Board Design

  • VCI 2Gbit SDRAMs

    • 256Mx8 (eight 64Mx4 stacked)

  • UTMC Serialized LVDS

    • 21 Data + Clock

  • ACTEL SX32s & 72s

    • Cpci core, SDRAM control, EDAC, data flow control, FIFOs, register files, etc…

11


Reconfigurable

Reconfigurable

  • Three operating modes under software control from the Instrument Controller

    • PPM, ping/pong memory mode

    • CMM, CPCI memory mode

    • MMM, memory maintenance mode

12


Ping pong mode

Ping/Pong Mode

SM I/F

16MHz, 16-bit LVDS

Memory A

256M x 16

Error corrected

SDRAM

Memory B

256M x 16

Error corrected

SDRAM

Bus master – DMA transfers

Switch memories under IC control

CPCI I/F

33MHz, 32-bit

13


Cpci memory mode

CPCI Memory Mode

256Mx32 Configuration

Memory A

256M x 16

Error corrected

SDRAM

Memory B

256M x 16

Error corrected

SDRAM

Bus target – R/W under IC control

CPCI I/F

33MHz, 32-bit

14


Memory maintenance mode

Memory Maintenance Mode

  • Built-in Self Test (BIST)

  • EDAC Reporting

  • Memory Scrubbing

15


Modes

Modes

16


Block diagram

Block Diagram

17


Lvds i f

LVDS I/F

18


Lvds control

LVDS Control

19


Input data paths

Input Data Paths

20


Memory modules

Memory Modules

21


Output data paths

Output Data Paths

22


Command config

Command & Config

23


Command config1

Command & Config

24


Command config2

Command & Config

25


Command config3

Command & Config

26


Mode control

Mode Control

27


Read control

Read Control

28


Cpci i f

CPCI I/F

29


Cpci control flow

CPCI Control Flow

30


A reconfigurable 1gb stacked sdram board

31


Summary

Summary

  • NASA LaRC is developing a 33MHz, 6U CPCI Gigabyte memory board for GIFTS and other space applications

  • The board design is reconfigurable as a ping/pong buffer or memory

  • The design makes extensive use of ACTEL FPGAs

  • Critical circuits prototyped, Design 80% complete

32


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