Chapter 4

1. Structure and Physical Operation I -V characteristics MOSFET DC circuits CMOS Inverter MOSFET amplifiers Biasing MOSFETS High Frequency MOS model SPICE MOSFET model parameters Chapter 4

2. MOSFET ID-VG, ID-VDS Output Charc. Input Charc. IDsat = n Cox W/L (VGS - VTN)2/2 --- SQUARE LAW L>250nm Subthreshold Leakage

3. MOSFET ID-VG, ID-VDS Output Charc. Input Charc. IDsat = vsat Cox W K (VGS - VTN) “Linear” L<250nm VTN Subthreshold Leakage

4. MOSFET ID-VG, ID-VDS Digital Logic Analog VTN VDD = 1

5. Anatomy of an Inverter PMOS NMOS PMOS Oxide NMOS

6. MOS Transistor Operating Regions VDD VDD

7. MOS Structure Symbols

8. MOS Transistor Operation

9. Triode or Linear Region OFF VGS < VT or VTO

10. Triode or Linear Region TRIODE VDS < VGS -VT

11. Increasing VDS – ID saturates

12. Increasing VDS – ID saturates

13. Cgs ON/Triode: V > 0 or VGS > VTO Cgs = WL Cox; V > VDS OFF: V < 0 or VGS < VTO Cgs  WL Cox Sat: V < 0 or VGS < VTO Cgs = 2/3 WL Cox ; V < VDS NMOS N Diffusion PMOS P Diffusion PolySilicon

14. Significant Process Parameter Constants

15. SPICE MODEL parameters Over 200 parameters define Modern 65nm MOSFETs 2000nm V = VGS-VT0 KP = Uo Cox

16. ID vs. VGS; VDS > V L > 250nm Square Law L < 250nm Vel. Sat.

17. ID vs. VGS; VDS > V Supplemental Taking the square root of ID and solving for slope & intercept; Extract VTO and KP

18. Enhancement/ Depletion Mode NMOS – 1st Quadrant PMOS – 3rd Quadrant Enhancement VTN > 0V VTP < 0V Depletion Mode VTN > 0V VTP < 0V

19. MOSFET parameters Ex -graphical ; V < VDS ID= W/LnCox (VGS - VTN)2/2 --- Sat. n Cox W/L =  ID = W/L n Cox {V VDS + VDS2/2}---Triode or Lin Region

20. CMOS Inverter – Strong pull up & down Rise time Fall Time

21. INVERTER POWER Supplemental

22. CMOS Logic

23. Why CMOS Inverter NMOS PMOS

24. CMOS Logic NMOS pull dwn Zbar = AB+CD

25. CMOS Logic PMOS pull UP Z = A’+B’  C’+D’

26. CMOS Logic PMOS pull UP Z = A’+B’  C’+D’

27. CMOS Logic PMOS pull UP Z = A’+B’  C’+D’ Supplemental

28. CMOS Logic Supplemental

29. CMOS Logic & Scaling If CL 3 minimum loads or 7.5fF 0.5um process OR 1.25fF 90nm process Note tr & tf NOT equal?

30. CMOS Logic & Scaling > 6-7X less Pwr

31. CMOS Logic NMOS pull DWN Z’ = A(D+E) + (BC) PMOS pull UP Z = [A+(D E)]  (B+C) PMOS pull UP Z = A’+B’ + C Supplemental NMOS pull DWN Z’ = ABC

32. Shifting the Qpt for Gain A Gain A = ΔVDS/ ΔVGS

33. CMOS Analog ID vs. VDS & rds Early Voltage and Lambda Take Away – effective output resistance Modeled by 1/ID or VA/ID

34. Modeling rout & gm

35. Developing the Bias Current • Setting biasing Current of Diff Amp, Note: • I R = ID6 • VDD -VSS= VSG + IB RB; R = (ß·2VDD - VTN) - (2·I))/(I·ß)

36. Diff Amp Current Behavior Starting Eq 1 & 2 Solving 1 & 2

37. Diff Amp Testing Case 1 Vin = 0, Io = 0 Case 2 -2xV < Vin < +2xV Case 3 Vin > | 2xV|; Io = IB

38. Diff Amp Voltage Behavior

39. Diff Amp Voltage Behavior

40. ID vs. VGS - ID vs. VDS; Amplification & gm

41. ID vs. VGS - ID vs. VDS; Amplification

42. Q pt Bias Stabilization Amplification

43. f1 Bias Considerations (Hi Pass) Amplification

44. f1 Bias Considerations(Hi Pass) Amplification

45. f2 Considerations(low pass) Amplification

46. Common Source Summary • Select Qpt = (VGS, ID, & VDS)and estimate gm and gds =ID/VA • Stabilize the Bias or Quiescent point – VGG =VGSQ + ID RS • RG1, RG2 and RS = VGSQ/IDQ VGG =VDD RG1/{RG1|| RG2} • Determine Cc1, Cc2, CS • Determine RD after finding gm and gds. • gain = -gm RD||rds||RL mid band gain • Generally – RL >> RD or rds & RG = RG||RG >> Rgen

47. Common Source Summary``

48. Biasing Example; GIVEN – Beta = 50mA/V, VT=0.7 & VA = 5, CISS = 1 pF Qpt is to be VGS = 1.0V, ID = 2.25mA, VGS /ID = 400 

49. Biasing Example; GIVEN – Beta = 50mA/V, VT=0.7 & VA = 5, CISS = 1 pF Qpt is to be VGS = 1.0V, ID = 2.25mA, VGS /ID = 400 

50. Biasing Example;