Low Emission Digital Circuit Design. Design-In for EMC on digital circuit. December 5th, 2005. Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS. Outline. Introduction 2. Logic family selection 3. Clock strategy selection SSCG - Delay cell array approach
Design-In for EMC on digital circuit
December 5th, 2005
2. Logic family selection
3. Clock strategy selection
SSCG - Delay cell array approach
4. Low noise power supply
(Static + Dynamic)
Target : Mixed-Mode Automotive Electronics Design
Key aspects : di/dt + Power + Area + Speed
But there is static power !!
Current Steering Logic
IT is a static power problem,
Switching off when standby ?
The curve of CSL 16-bit RCA was obtained
by calculating the real speed F of the circuit,
given the different supply current I.
M1 > M3
is really difficult ,process dependent
[Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's]
Fig.3 E-CSL inverter
Fig.4 power vs. frequency
Fig.5 di/dt vs. frequency
MAX di/dt change
MIN di/dt change
Fig.6 di/dt vs. process corner
Winner is E-CSL
1. Deviating the period of the clock signal from its fundamental by a small percentage(usually +/- 1% ) and in a predictable fashion(usually Triangular modulation profile )
2. The total power of the clock signal remains the same.
1. PLL-SSCG: VCO has its input voltage controlled by a modulation waveform.
2. DCA-SSCG: By controlling the temporal spacing of the edges, the clock’s frequency is indirectly controlled
[Keith B. Hardin, Spread Spectrum Clock Generation for the Reduction of Radiated Emissions]
Disadvantage of PLL-SSCG:
Advantage of DCA-SSCG
Each delay cell comprised of delay element and a positive latch:
Delay Cell #1
Delay Cell #2
Delay Cell #N
Delay Cell Control
SSC: f0 + ∆f
Result: Edge-to-edge jitter varied in deterministic fashion.
Our results show:
However 2 problems still remain:
?? Is there any global approach ??
Thank you for your attention