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Low Emission Digital Circuit Design. Design-In for EMC on digital circuit. December 5th, 2005. Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS. Outline. Introduction 2. Logic family selection 3. Clock strategy selection SSCG - Delay cell array approach

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Low emission digital circuit design
Low Emission Digital Circuit Design

Design-In for EMC on digital circuit

December 5th, 2005

Junfeng Zhou

Wim Dehaene

KULeuven ESAT-MICAS


Outline
Outline

Introduction

2. Logic family selection

3. Clock strategy selection

SSCG - Delay cell array approach

4. Low noise power supply


Part i introduction
Part I: Introduction

  • Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for high speed digital circuit,

  • Most of them are due to power and ground fluctuation.

  • Although the detailed calculation of EMI noise is rather difficult , we can use the di/dt as the index, since the current loop contributes the EMI.


Part 2 logic family selection
Part 2: Logic Family Selection

PNMOS

RSBCMOS

SCMOS

MCML

FSCL

CSL


Comparison of di dt power and area
Comparison of di/dt ,power and area

(Static + Dynamic)

Target : Mixed-Mode Automotive Electronics Design

Key aspects : di/dt + Power + Area + Speed

Ring Oscillator

of 21-stages

But there is static power !!

Current Steering Logic


Detailed comparison of csl and scmos
Detailed comparison of CSL and SCMOS

CSL

One-bit Adder

IT is a static power problem,

Switching off when standby ?

Note:

The curve of CSL 16-bit RCA was obtained

by calculating the real speed F of the circuit,

given the different supply current I.



Problem with csl
Problem with CSL

  • Mismatch sensitive, annoying for standard cells

  • rather slow/power hungry

  • Not full swing

Matching required!

M1 > M3


Can we do it better
Can we do it better ?

CBL

C-CBL:

  • sizing for optimal current balance

    is really difficult ,process dependent

[Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's]


Solution enhanced current steering logic
Solution- Enhanced current steering logic

  • Still current source basing

  • Increase in logic level, hence increase the robustness

  • Reduced output capacitance, hence the speed is increased

Minimum size

Fig.3 E-CSL inverter


Comparison of csl c cbl ecsl and scmos
Comparison of CSL, C-CBL, ECSL and SCMOS

Ring Oscillator

of 21-stages

Fig.4 power vs. frequency

Fig.5 di/dt vs. frequency


Di dt performance vs process variation
di/dt performance vs. process variation

MAX di/dt change

MIN di/dt change

Ring Oscillator

of 21-stages

Fig.6 di/dt vs. process corner


Conclusion of low noise logic families
Conclusion of Low noise Logic Families

  • CSL,E-CSL show a smaller area per logic function for complex digital gates and systems compared to SCMOS logic technique.

  • Current source ensures the major di/dt reduction,

  • Process variation sensitivity also becomes better due to the dominance of current source,

  • E-CSL gives comparable di/dt performance with CSL,

  • E-CSL is Faster and Less power consuming than CSL due to the lower area and lower capacitance.

  • Static power consumption remains the challenge for wide application of the CSL,E-CSL technique in very large digital systems. Can be solved by using power down strategies, which is highly application dependent

Winner is E-CSL


Part ii clock strategy sscg
Part II: Clock strategy (SSCG)

1. Deviating the period of the clock signal from its fundamental by a small percentage(usually +/- 1% ) and in a predictable fashion(usually Triangular modulation profile )

2. The total power of the clock signal remains the same.

Implementation:

1. PLL-SSCG: VCO has its input voltage controlled by a modulation waveform.

2. DCA-SSCG: By controlling the temporal spacing of the edges, the clock’s frequency is indirectly controlled

[Keith B. Hardin, Spread Spectrum Clock Generation for the Reduction of Radiated Emissions]


Sscg pll vs dca
SSCG - PLL vs. DCA ?

Disadvantage of PLL-SSCG:

  • Basically analog circuit(VCO, charge pump, loop filter), more susceptible to noise

  • PLL-SSCG suffers from the drawback of reduction in maximum achievable EMI reduction due to the inherent random jitter of the circuitry(due to thermal noise, flicker noise).

  • Leads to large jitter in clock which is unacceptable

    Advantage of DCA-SSCG

  • Digital circuits, good immunity to noise.

  • Leads to smaller random jitter, simpler implementation and reduction in area

  • The reduction in variance of unintentional jitter is key to the delay cell array technique being able to achieve greater reduction in EMI.


Sscg dca how does it work
SSCG-DCA: How does it work?

Each delay cell comprised of delay element and a positive latch:

Q

Q

Q

D

D

D

EN

EN

EN

Delay Cell #1

Delay Cell #2

Delay Cell #N

Delay Cell Control

Q T

T Flip-Flop

N/2

Counter

f0

SSC: f0 + ∆f

Result: Edge-to-edge jitter varied in deterministic fashion.


Clock attenuation
Clock Attenuation

Our results show:

  • Dominant power in odd harmonics

  • DCA-SSCG:

    • Delay cell based SSCG implemented shows low power and simple circuit implementation

    • 8dBof clock attenuation on fundamental

    • Improved design can be achieved by using differential delay cell element


Part iii low noise power supply design
Part III: Low Noise Power supply design

However 2 problems still remain:

  • Static power consumption

  • New logic family standard cell must be designed and

    characterised

?? Is there any global approach ??


Questions
Questions

Thank you for your attention


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