65nm cmos activities at lal lapp
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65nm CMOS activities at LAL/LAPP. Abdenour Lounis , LAL Orsay Gisèle Martin, Damien Thienpont, Jeanne Tongbong OMEGA Renaud Gaglione , Richard Hermel LAPP Annecy Presented by Jean-Francois Genat LPNHE Paris 2d AIDA Annual Meeting April 10th 2013 LNF Frascati.

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65nm CMOS activities at LAL/LAPP

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65nm cmos activities at lal lapp

65nm CMOS activitiesat LAL/LAPP

Abdenour Lounis,

LAL Orsay

Gisèle Martin, Damien Thienpont, Jeanne Tongbong

OMEGA

Renaud Gaglione, Richard Hermel

LAPP Annecy

Presented by Jean-FrancoisGenat

LPNHE Paris

2d AIDA Annual Meeting

April 10th 2013 LNF Frascati


Lal lapp 65 nm projects

LAL/LAPP 65 nm projects

  • IP blocks for WP3.3

  • LAL -> Pixel (LAL/LPNHE)

  • -> OTA (Analog low noise Front-end)

  • -> PLLs

  • LAPP -> LAL Omegapix

  • -> DAC 12b 80 MHz -> 14b

  • -> Clusters centroid evaluation

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Pixels readout

Pixels readout

Two options:

-1 In-pixel circular buffer

-2 Use in-pixel storage (FIFOs) instead of circular buffer to reduce

power and Silicon area

  • Hit times are recorded for the L1 latency

  • At L1, hit times in FIFOs are compared to the current time and

  • selected for L2 if hit time matches L1 time

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Pixels readout on pixel circular buffer vs on pixel fifos

Circular buffer schemeSelectivereadoutscheme

Pixel hit

Pixel hit

Current time

(8-bit)

Pixels readout: on-pixel Circular buffer vs on-pixel FIFOs

120-deep

Circular

Memory

Use the same

Dynamic Memory Cell

Beam

Crossing

Dynamic

Memory

Pixel

FIFO depth 16

Selectivereadoutscheme: Save silicon area and power at the pixel level

Current time - 120

L1 Trigger

L1 Trigger

Readout

Readout

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Timing based pixels sparse scan readout

Extract a stack of addresses of pixels

hit in time with L1

Timing based pixels sparse scan readout

- A pixel switchisopen on a hit

- At L1, eachreadclock cycle outputs the address of a pixel with a hit time matchingthis L1, fromcolum top to bottom

- The read pixel switchisclosedafterread

- The next hit pixel (switch open) isread

Scan all columns in parallel

to end of columnFIFOs

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Building block

in

Building block

Output bus

L1 latency

ck

FIFO depth

L1

  • VHDL model OK

  • - Cellslibrary 65nm TSMC

  • - I/O locations file (x,y in microns) text file

  • - Dimensions (FIFO depth 16) 35 x 70 mm2

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Layout in tsmc 65nm

Layout in TSMC 65nm

Design kit

FromEuropractice

Waiting CERN

contractwith TSMC

FIFO depth 24

35 x 90 mm2

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Plls clock recovery

PLLs (clockrecovery)

Used as frequencysynthesizers

Charge pump PLL (CP-PLL)

CP –PLL for frequency multiplication

Low power , lowjitter , fullyintegrated

TypicalInput frequency : 40 MHz

Output frequency range: 80 MHz-320 MHz

SlidefromJeanne Tongbong (LAL Orsay)

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


65nm cmos activities at lal lapp

PLLs (clockrecovery)

c

Ring oscillator

Status: OMEGA develops

PLL block in 350nm as a

debugging block

Simulations going on in 65nm

AwaitingCERN design kit

ChagePump(CP) / LoopFilter (LP)

Phase Frequency Detector (PFD)

PFD-CP-LP basic implementation

SlidefromJeanne Tongbong (OMEGA)

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Lapp involvement

LAPP is strongly involved in the HL-LHC tracker upgrade (services, ALPINE design, cooling) and aims to be involved in tracker-related micro-electronics developments.

support to OMEGA ;

support to CPPM and FEi5 design.

→ LAPP team works on 65nm building blocks for future trackers which may be included in tracker readout chip.

LAPP involvement

SlidefromRenaud Gaglione LAPP

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


Developments

Developments

  • Present:design ofa capacitive 12 bits DAC for CPPM 12 bits SAR GADC. 1V, 1MHz, ~mW

  • Soon: specs and design of comparator for CPPM SAR GADC and for LAL Wilkinson ADC;

  • Considered: JTAG block.

SlidefromRenaud Gaglione LAPP

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


The end

The end...

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


65 nm omegapix2

65 nm OMEGAPIX2

A new OMEGAPIX chip in 65 nm techno as an alternative to the 3D chip

Same pixel form factor: 35x200 μm

New analog front-end (LAL), new digital pixel (LPNHE)

TSMC 65 nm techno

3x1z1u metal stack (RF, CRN65LP), 6 metal layers + RDL

tcbn65lp standard cells library

In waiting for the common PDK provided by CERN

SlidefromD. Thienpont, J. Tongbong


Via last aida project lal lpnhe lapp

Sensor + Readout chip in 65nm

Via Last AIDA project: LAL + LPNHE+ LAPP

TSVs module

back side

front side

front end chip (65 nm)

First proposal

100 μm

front side

back side

100 μm

TSV

front end chip (65 nm)

Bonding …

Bumpbonding

150 μm or less

Interconnexions

sensor

150 μm or less

sensor

HV

HV

second proposal

SlidefromAbdenour Lounis (IN2P3 LAL Orsay)

Jean-Francois Genat , April 10th 2013, INFN LNF Frascati


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