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We rd1 rd2 z - PowerPoint PPT Presentation

Digital Design Using Verilog

ILL. 1. 2. 0. PCSEL. 3. 4. XAdr. OP. JT. 00. Instruction. A. Memory. PC. D. +4. RA2SEL. Rc: <25:21>. Ra: <20:16>. Rb: <15:11>. 1. 0. +. WASEL. W. E. R. F. RA1. Register. RA2. XP. 1. WD. Rc: <25:21>. WA. WA. File. 0. WE. RD1. RD2. Z. Z. JT.

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We rd1 rd2 z - PowerPoint PPT Presentation

Digital Design Using Verilog