'Mips processors' presentation slideshows

MIPS assembly

409 views • 28 slides

Chapter Six

Chapter Six. Pipelining: Overview. Pipelining. Improve performance by increasing instruction throughput. Pipelining. Improve performance by increasing instruction throughput Ideal speedup is number of stages in the pipeline. Do we achieve this?. single-cycle vs. pipelined performance.

509 views • 27 slides

Final Presentation

Final Presentation. Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL. Students: Danny Hofshi, Shai Shachrur Supervisor: Mony Orbach. Winter 2012. What we did ?. FPGA. C++ Perl. Bluespec Scemi. Bluespec HDL. MIPS. Xilinx FPGA.

346 views • 23 slides