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Clock slew - PowerPoint PPT Presentation

Clock Issues in Deep Submircron Design

Clock Issues in Deep Submircron Design. 1999. 10 Jun Dong Cho Sungkyunkwan Univ. Dept. ECE Mail : Jdcho@skku.ac.kr Homepage : vada.skku.ac.kr. Agenda. The Issues of Clock Tree Synthesis The Basic Consideration of Clock Tree Synthesis Traditional Clock Routing Algorithm

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877 views • 50 slides

Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs

Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs. Xin Zhao and Sung Kyu Lim School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia, U.S.A. Reference the slides of this paper in ASPDAC 2010. Outline.

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597 views • 38 slides

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Clock slew - PowerPoint PPT Presentation

Clock Issues in Deep Submircron Design

Power and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) based 3D ICs