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Device and Architecture Co-Optimization for FPGA Power Reduction

Device and Architecture Co-Optimization for FPGA Power Reduction. Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, and Prof. Lei He EE Department, UCLA Partially supported by NSF CAREER award CCR-0093273/0401682 and NSF grant CCR-0306682. Address comments to lhe@ee.ucla.edu. Outline.

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551 views • 38 slides

A First-step Towards an Architecture Tuning Methodology for Low Power

A First-step Towards an Architecture Tuning Methodology for Low Power. Roman Lysecky Department of IP Management Conexant Newport Beach. Greg Stitt, Frank Vahid*, Tony Givargis Dept. of Computer Science & Engineering University of California, Riverside

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179 views • 17 slides

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Architecture tuning - PowerPoint PPT Presentation

Device and Architecture Co-Optimization for FPGA Power Reduction

A First-step Towards an Architecture Tuning Methodology for Low Power