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LOGIC SIMULATION AND FAULT DIAGNOSIS

LOGIC SIMULATION AND FAULT DIAGNOSIS. BY JINS DAVIS ALEXANDER ELEC 7250 PRESENTATION. PROBLEM STATEMENT. To write a logic simulator to verify combinational circuits given a set of input vectors and the expected output responses.

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264 views • 11 slides

University of Strathclyde Department of Electronic and Electrical Engineering

University of Strathclyde Department of Electronic and Electrical Engineering 204, George Street, Glasgow G1 1XW, UK URL: www.eee.strath.ac.uk Email: Fault-Locator@eee.strath.ac.uk Tel: +44 (0)141 548 2587.

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211 views • 10 slides

Integer ALU2

Crash Dump File (e.g ., crash state and inputs). Isolate Instructions First Affected by the Fault. Identify Erroneous Data. Identify Instructions that Change Erroneous Data. Diagnosing Intermittent Faults Using Software Techniques

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116 views • 1 slides

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Actual fault - PowerPoint PPT Presentation

LOGIC SIMULATION AND FAULT DIAGNOSIS

University of Strathclyde Department of Electronic and Electrical Engineering

Integer ALU2