Volume 7 issue 1 april 2010 presented by shilpa casula
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A Power aware mapping approach to map IP cores onto NOCs under bandwidth and latency constraints XIAO HANG WANG ,MEI YANG,YINGTAO JIANG &PENG LIU. Volume 7,Issue 1,April 2010 Presented by SHILPA CASULA. INTRODUCTION.

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Volume 7 issue 1 april 2010 presented by shilpa casula

A Power aware mapping approach to map IP cores onto NOCs under bandwidth and latency constraints XIAO HANG WANG ,MEI YANG,YINGTAO JIANG &PENG LIU

Volume 7,Issue 1,April 2010

Presented by SHILPA CASULA


Introduction
INTRODUCTION under bandwidth and latency constraints

  • We are investigating the IP mapping problem by mapping a set of IP cores onto the tiles of a mesh based Network-on-Chip (NoC) architecture.

  • Power consumption due to intercore communications should be minimized.

  • This problem is considered under both bandwidth and latency constraints.


Now for a target application to run on a NoC based MPSoC architecture, a 3 step design flow is followed.

  • A target application is partitioned into multiple concurrent tasks.


  • The tasks are scheduled and allocated to selected IP cores. architecture, a 3 step design flow is followed.

  • Then the IP cores are optimally mapped onto the Noc based MPSoc architecture in terms of power, performance under the constraints of latency or bandwidth.

    After mapping, all the routing paths between any pair of communication IP cores are optimally identified.


TEM ALGORITHM architecture, a 3 step design flow is followed.

  • Generates high mapping results with low runtime.

  • Achieves significant improvement over MOCA in terms of runtime and quality solutions.

  • Compared with BNB it produces results of same quality but with less CPU time.


Related research
RELATED RESEARCH architecture, a 3 step design flow is followed.

BRANCH AND BOUND(HU and MARCULESCU 2005)

  • With large queue size, it demands high memory and more CPU time.

  • Feasible for mapping IP cores with fairly small size.

  • Since the work queue is small, most solutions are trimmed off.

    GREEDY BASED HEURISTIC ALGORITHM( Murali and De Micheli 2004)

  • Very low runtime but often sacrifice the quality of solutions.

  • If properly designed, degradation of the solution is minimized.

  • IP cores with demanding communication requests should be mapped first to reduce overall power consumption.


SA/GA/TS ALGORITHMS architecture, a 3 step design flow is followed.(HARMANI & FARAH 2008,LU 2008)

  • IP mapping can be done in divide and conquer like manner

  • High quality solutions are not guaranteed.

  • Require longer time than Greedy Based mapping algorithm.

    LINEAR PROGRAMMING ALGORITHM(MURALI AND DE MICHELI 2004)

  • Computation is time consuming and no guarantee for high quality solutions.


Approach
APPROACH architecture, a 3 step design flow is followed.

PROBLEM FORMULATION AND POWER MODEL


  • The power model used in architecture, a 3 step design flow is followed.Hu and Marculescu in 2005 is followed in this study.

  • Bit power(E bit)is defined as the power consumed when 1 bit of data is transported through a router. It is given as


Problem Description architecture, a 3 step design flow is followed.

  • Assumption: Before IP mapping is performed, a given application is already bounded and scheduled onto a list of selected IP cores.

  • The communication patterns between any pair of IP cores are modeled by target applications CTG.

  • Whereas the Noc architecture that the application will be mapped onto is described in terms of ACG.


Classification of applications: architecture, a 3 step design flow is followed.

Template 1: An application falls into template 1(tightly coupled) if there there is atleast one hot node in its CTG.

Template 2: An application falls into template 2 (distributed) if there is no hot nodes in its CTG.


Mapping algorithm for tem
MAPPING ALGORITHM FOR TEM architecture, a 3 step design flow is followed.

Input

1)CTG of an application

2)ACG of an NoC Architecture

3)E,A sorted edge list of CTG

Output

1)MAP1: The table storing the mapping results for each IP core

Function

Map the application(CTG) onto the NoC architecture(ACG) and allocate routing paths.


Mapping algorithm for template1
MAPPING ALGORITHM FOR TEMPLATE1 architecture, a 3 step design flow is followed.

Input

1)CTG of an application

2)ACG of an NoC Architecture

3)A sorted edge list of CTG

4)The set of hot nodes.

Output

1)MAP 2: The table storing the mapping results for each IP core.

Function

Map the application of template1 onto the NoC architecture


Mapping algorithm for template 2
MAPPING ALGORITHM FOR TEMPLATE 2 architecture, a 3 step design flow is followed.

Input

1)CTG of an application

2)ACG of an NoC Architecture

Output

1)MAP 2: The table storing the mapping results for each IP core.

Function

Map the application of template2 onto the NoC architecture


Routing path allocation
ROUTING PATH ALLOCATION architecture, a 3 step design flow is followed.

  • Next step after mapping is routing path allocation.

  • In NoC design ,the deterministic and static routing is preferred due to its simplicity.

  • All the routing paths have to be minimal and the resulting network has to be deadlock free.

  • Bandwidth and latency constraints need to be satisfied.


Performance evaluation
Performance Evaluation architecture, a 3 step design flow is followed.

  • To evaluate the performance of TEM algorithm,template1 and template 2 algorithms are implemented and simulated

  • BNB and MOCA are also implemented .

  • Mapping results of all the 3 algorithms are compared.

  • Random and multimedia applications are adopted as benchmarks.


Experiments on random applications and their results
Experiments on Random Applications and their Results architecture, a 3 step design flow is followed.


Experiments on multimedia benchmarks and their results
Experiments on Multimedia Benchmarks and their results architecture, a 3 step design flow is followed.


  • The multimedia system(MMS) benchmark is also simulated on a mesh based NoC.

  • Table 6 shows the reduction in power consumption of TEM over MOCA.

  • On average, the degradation of TEM over BNB is within 10% for both XY and Odd-Even routing.

  • With latency constraints, the power consumption of TEM is slightly lower than MOCA.


Conclusion and future research
CONCLUSION AND FUTURE RESEARCH mesh based NoC.

  • This article presented a Template based greedy algorithm to address the IP mapping problem.

  • Application falls into template 1 if there are 1 or more hot nodes.

  • Application falls into Template 2 if the communications are nearly evenly distributed among the vertices.

  • The experiment results showed that TEM generates high quality mapping results with low runtimes.

  • Future work includes extension of TEM to folded torus, fat tree and other NoC topologies.


Questions
Questions???? mesh based NoC.


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