Motivation for CDR: Deserializer (1)

1. Motivation for CDR: Deserializer (1) Input data Input clock 1:2 DMUX 1:2 DMUX channel 1:2 DMUX If input data were accompanied by a well-synchronized clock, deserialization could be done directly. Prof. M. Green / Univ. of California, Irvine

2. Motivation for CDR (2) Clock Data retimed data Clock Recovery circuit input data recovered clock PLLs naturally provide synchronization between external and internal timing sources. A CDR is often implemented as a PLL loop with a special type of PD... • Providing two high-speed channels (for data & clock) is expensive. • Alignment between data & clock signals can vary due to different channel characteristics for the different frequency components. Hence retiming would still be necessary. Prof. M. Green / Univ. of California, Irvine

3. f f RZ spectrum has energy at 1/Tb conventional phase detector can be used. NRZ spectrum has null at 1/Tb ?? Return-to-Zero vs. Non-Return-to-Zero Formats NRZ Tb RZ 0 1 0 1 1 1 0 Prof. M. Green / Univ. of California, Irvine

4. Vdata Vd VRCK Phase Detection of RZ Signals Vdata VRCK Vd • Phase detection operates same as for clock signals for logic 1. • Vd exhibits 50% duty cycle for logic 0. • Kpd will be data dependent. Prof. M. Green / Univ. of California, Irvine

5. Vdata Vd VRCK • RZ signals can use same phase detector as clock signals • RZ data path circuitry requires bandwidth that is double that of NRZ. • Different type of phase detection required for NRZ signals. Phase Detection of NRZ Signals Vdata VRCK Vd Since data rate is half the clock rate, multiplying phase detection is ineffective. Prof. M. Green / Univ. of California, Irvine

6. Idea: Mix NRZ data with delayed version of itself instead of with the clock. Example: 1010 data pattern (differential signaling) Tb X X = = fundamental generated Prof. M. Green / Univ. of California, Irvine

7. QI QI D CK CK CK CK CK CK CK CK latch: CK Q D CK CK CK Slave Master Operation of D Flip-Flips (DFFs) DFF: CMOS transmission gate: Ideal waveforms: Symbol: D0 D1 D2 D D Q CK Q D0 D1 D2 No bubble  Q changes following rising edge of CK Prof. M. Green / Univ. of California, Irvine

8. DFF Setup & Hold Time At CK rising edge, the master latches and the slave drives. D tsetup thold CK Q When a data transition occurs within the setup & hold region, metastability occurs. Prof. M. Green / Univ. of California, Irvine

9. QI CK CK CK CK D0 D1 D2 D CK Q D CK CK CK D1 D2 D0 Q CK Slave Master tck-q DFF Clock-to-Q Delay tck-q is determined by delays of transmission gate and inverter. Prof. M. Green / Univ. of California, Irvine

10. P Din Q RCK synchronized: RCK RCK early: D3 D2 D0 D1 D3 D0 D1 D1 D3 D2 D2 D3 D0 D1 D0 D2 Delay between Din to Q is related to phase between Din & RCK Realization of Data/Data Mixing : Same as Din, synchronized with RCK Din RCK Q P D0 D1 D2 D3 D0 D1 D2 D3 D1 D2 D3 D4 D1 D2 D3 D4 Prof. M. Green / Univ. of California, Irvine

11. RCK early ( < 0): Dt Tb Define zero phase difference as a data transition coinciding with RCK falling edge; i.e., RCK rising edge is in center of data eye. RCK synchronized ( = 0): Din RCK Q P Dt Tb Prof. M. Green / Univ. of California, Irvine

12. Phase detector characteristic also depends on transition density: P Din Q RCK 0011… pattern: 0101… pattern: Din RCK Q P Vswing In general, where average transition density Prof. M. Green / Univ. of California, Irvine

13. Constructing CDR PD Characteristic -p +p a = 1 Df slope: a = 0.5 intercept: a = 0.25 Both slope and offset of phase-voltage characteristic vary with transition density! Prof. M. Green / Univ. of California, Irvine

14. To cancel phase offset: P Q Din Q RCK RCK QR R D0 D0 D2 D1 D1 D3 D2 D3 R QR Always 50% duty cycle; average value is +1/2  = 1 Kpd still varies with , but offset variation cancelled.  = 0.5 -p +p -1/2 C. R. Hogge, “A self-correcting clock recovery circuit,” IEEE J. Lightwave Tech., vol. 3, pp. 1312-1314, Dec. 1985. Prof. M. Green / Univ. of California, Irvine

15. Transconductance Block Iout+ Iout- P+ P- R- R+ ISS ISS Prof. M. Green / Univ. of California, Irvine

16. Due to inherent mixing operation, Hogge PD is not a good frequency detector. A frequency acquisition loop with a reference clock is usually needed: J. Cao et al., “OC-192 transmitter and receiver in 0.18m CMOS,” JSSC. vol. 37, pp. 1768-1780, Dec. 2002. Prof. M. Green / Univ. of California, Irvine

17. Non-Idealities in Hogge Phase Detector:A. Clock-to-Q Delay (1) P Din Q RCK tck-Q R QR tck-Q Prof. M. Green / Univ. of California, Irvine

18. Non-Idealities in Hogge Phase Detector:A. Clock-to-Q Delay (2) Result is an input-referred phase offset: Din RCK +a/2 tck-Q fos Q -a/2 tck-Q QR P R Prof. M. Green / Univ. of California, Irvine

19. Non-Idealities in Hogge Phase Detector:A. Clock-to-Q Delay (3) tck-Q Din RCK Dout Phase offset moves RCK away from center of data, making retiming less robust. Din CDR RCK Prof. M. Green / Univ. of California, Irvine

20. Din DDt RCK Q QR P R Non-Idealities in Hogge Phase Detector:A. Clock-to-Q Delay (4) Use a compensating delay: Set Dt Dt P Din Q RCK tck-Q R QR tck-Q Prof. M. Green / Univ. of California, Irvine

21. P Din Q Din RCK RCK R Q QR QR P R P and R are offset by 1/2 clock period Non-Idealities in Hogge Phase Detector:B. Delay Between P & R (1) Prof. M. Green / Univ. of California, Irvine

22. Non-Idealities in Hogge Phase Detector:B. Delay Between P & R (2) P R Average value of Vcontrol is well-controlled, but resulting ripple causes high-frequency jitter. P Vcontrol Din Q RCK to VCO R QR Prof. M. Green / Univ. of California, Irvine

23. Non-Idealities in Hogge Phase Detector:B. Delay Between P & R (3) Idea: Based on R output, create compensating pulses: Standard Hogge/charge pump operation for single input pulse: Din RCK DFF Din RCK latch Q QR P (up) latch R (dn) Vcontrol latch Prof. M. Green / Univ. of California, Irvine

24. Non-Idealities in Hogge Phase Detector:B. Delay Between P & R (4) Cancels out effect of next pulse Din Din RCK Q1 RCK Q1 DFF Q2 Q3 Q2 latch Q4 P (up) Q3 R (dn) latch P’(dn) R’(up) Q4 latch Vcontrol Prof. M. Green / Univ. of California, Irvine

25. 60 40 20 response from ideal linear PD PD Differential Output (mV) 0 -20 -40 -60 simulated result of one linear PD -50p -40p -30p -20p -10p 0 10p 20p 30p 40p 50p Data Delay in regard to Clock (s) Other Nonidealities of Hogge PD (1) Prof. M. Green / Univ. of California, Irvine

26. Other Nonidealities of Hogge PD (2) Effect of Transition Density: Prof. M. Green / Univ. of California, Irvine

27. Other Nonidealities of Hogge PD (3) Effect of DFF bandwidth limitation: Prof. M. Green / Univ. of California, Irvine

28. Other Nonidealities of Hogge PD (4) Effect of XOR bandwidth limitation: Since the PD output signals are averaged, XOR bandwidth limitation has negligible effect. Prof. M. Green / Univ. of California, Irvine

29. Other Nonidealities of Hogge PD (5) Effect of XOR Asymmetry: Prof. M. Green / Univ. of California, Irvine

30. Ideal binary phase-voltage characteristic: Also known as “bang-bang” phase detector +1/2  -1/2 Binary Phase Detectors Idea: Directly observe phase alignment between clock & data Clock falling edge late: Increase Vcontrol Clock falling edge centered: No change to Vcontrol Clock falling edge early: Decrease Vcontrol Prof. M. Green / Univ. of California, Irvine

31. Top (bottom) DFF detects on Din rising (falling) edge; DFF selected by opposite Din edge to avoid false transitions due to clock-q delay. Realization using double-clocked DFF; note that RCK/Din connections are reversed: VP RCK = RCK VP D Flip-Flop as Phase Detector Din Early clock: Data transitions align with clock low RCK Din Late clock: Data transitions align with clock high RCK Prof. M. Green / Univ. of California, Irvine

32. tsetup • If transition at D input occurs within setup/hold time, metastable operation results. • Q output can “hang’’ for an arbitrarily long time if zero crossings of D & CK occur sufficiently close together. • Metastable operation is normally avoided in digital circuit operation(!) thold D CK Q What happens if Df=0? Prof. M. Green / Univ. of California, Irvine

33. Dog Dish Analogy A dog placed equidistant between two dog dishes will starve (in theory). ? ? ? Prof. M. Green / Univ. of California, Irvine

34. Non-Idealities in Binary DFF Phase Detector RCK VP Metastable operation difficult to characterize & simulate, varies widely over processing/temperature variations. Kpd (and therefore jitter transfer function parameters) are difficult to analyze. Exact value of Kpd depends on metastable behavior and varies with input jitter. Large-amplitude pattern-dependent variation is present in phase detector output while locked. During long runs phase detector output remains latched, resulting in VCO frequency changing continuously: Prof. M. Green / Univ. of California, Irvine

35. Circuit realization should sample data with clock (instead of clock with data) while maintaining bang-bang operation. Idea: Change VCO frequency for only one clock period RCK VP RCK early RCK late Prof. M. Green / Univ. of California, Irvine

36. RCK Q1 Q2 Q3 Q4 DN UP RCK early Q1 leadsQ3;Q2/Q4 in phase RCK late Q3 leadsQ1;Q1/Q4 in phase DN Alexander Phase Detector UP Q2 Q1 Q3 Q4 RCK Prof. M. Green / Univ. of California, Irvine

37. Simulation Results: Alexander PD DFF outputs VCO control voltage Prof. M. Green / Univ. of California, Irvine

38. Simulation Comparison: Linear vs. Binary Vcontrol Vcontrol Binary PD Linear PD • very small freq. acquisition range • low steady-state jitter • high freq. acquisition range • high steady-state jitter Prof. M. Green / Univ. of California, Irvine

39. Half-Rate CDRs To relax speed requirements for a given fabrication technology, a half-rate clock signal can be recovered: input data Din RCK full-rate recovered clock RCK2 half-rate recovered clock • Can be used in in applications (e.g., deserializer) where full-rate clock is not required. • Duty-cycle distortion will degrade bit-error ratio & jitter tolerance compared to full-rate versions. Prof. M. Green / Univ. of California, Irvine

40. Din DA RCK2 DB RCK2 Din D0 D1 D2 D3 D4 DA D2 D4 D0 synchronized with clock transitions DB D3 D1 Idea 1: Input data can be immediately demultiplexed with half-rate clock Prof. M. Green / Univ. of California, Irvine

41. These pulse widths contain phase information. Din XA DA Splitting D flip-flops into individual latches: RCK2 latch latch XB DB latch latch RCK2 Din XA synchronized with both RCK2 & Din XB DA synchronized with RCK2 DB Prof. M. Green / Univ. of California, Irvine

42. Complete Linear Half-Rate PD RCK2 XA DA Din Din RCK2 P R XA XB DB XB DA J. Savoj & B. Razavi, “A 10Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,” JSSC, vol. 36, pp. 761-768, May 2001. DB Prof. M. Green / Univ. of California, Irvine

43. Din Din RCK RCK RCKQ RCKQ S0 S1 S2 S0 S1 S2 Clock early Clock late Phase logic: S0, S2 sampled with RCK transitions S1 sampled with RCKQ transitions clock early clock late no transition Idea 2: Observe timing between Din, RCK and quadrature RCKQ Prof. M. Green / Univ. of California, Irvine

44. DI Din VPD RCK DQ J. Savoj & B. Razavi, “A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase detector,” JSSC, vol. 38, pp. 13-21, Jan. 2003. RCKQ Din Din RCK RCK RCKQ RCKQ DI DI DQ DQ VPD VPD Clock early Clock late Prof. M. Green / Univ. of California, Irvine

45. DLL-Based CDRs phase generator fck fref CMU phase MUX VC PD Din C Dout retimer • CMU JBW can be optimized to minimize fck jitter. • No VCO inside CDR loop; less jitter generation. • Can be arranged to have faster lock time. CDR loop Prof. M. Green / Univ. of California, Irvine

46. Fast-Lock CDR for Burst-Mode Operation EN CDR based on 2 gated ring oscillators: Each ring oscillation waveform is forced to sync with one of the Din phases. Din RCK Gated ring oscillator: EN high: 7-stage ring oscillator EN low: no oscillation Prof. M. Green / Univ. of California, Irvine