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4446 Design of Microprocessor-Based Systems. Serial Interface. Dr. Esam Al_Qaralleh CE Department Princess Sumaya University for Technology. External Interface. Two ways of interfacing I/O devices Serial Cheaper Slower Parallel Faster Data skew. Limited to small distances.

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slide1

4446 Design of Microprocessor-Based Systems

Serial Interface

Dr. Esam Al_Qaralleh

CE Department

Princess Sumaya University for Technology

external interface
External Interface
  • Two ways of interfacing I/O devices
    • Serial
      • Cheaper
      • Slower
    • Parallel
      • Faster
      • Data skew

Limited to small distances

external interface cont d
External Interface (cont’d)

Two basic modes of data transmission

external interface cont d1
External Interface (cont’d)
  • Serial transmission
    • Asynchronous
      • Each byte is encoded for transmission
        • Start and stop bits
      • No need for sender and receiver synchronization
    • Synchronous
      • Sender and receiver must synchronize
        • Done in hardware using phase locked loops (PLLs)
      • Block of data can be sent
      • More efficient
        • Less overhead than asynchronous transmission
      • Expensive
external interface cont d3
External Interface (cont’d)

Asynchronous transmission

external interface cont d4
External Interface (cont’d)
  • EIA-232 serial interface
    • Low-speed serial transmission
    • Adopted by Electronics Industry Association (EIA)
      • Popularly known by its predecessor RS-232
    • It uses a 9-pin connector DB-9
      • Uses 8 signals
    • Typically used to connect a modem to a computer
external interface cont d5
External Interface (cont’d)
  • Transmission protocol uses three phases
    • Connection setup
      • Computer A asserts DTE (Data Terminal Equipment) Ready
        • Transmits phone# via Transmit Data line (pin 2)
      • Modem B alerts its computer via Ring Indicator (pin 9)
        • Computer B asserts DTE Ready (pin 4)
        • Modem B generates carrier and turns its DCE (Data Communication Equipment) Ready
      • Modem A detects the carrier signal from modem B
        • Modem A alters its computer via Carrier Detect (pin 1)
        • Turns its DCE Ready
    • Data transmission
      • Done by handshaking using
        • request-to-send (RTS) and clear-to-send (CTS) signals
    • Connection termination
      • Done by deactivating RTS
slide9

Start

bit

B0

B1

B2

B3

B4

B5

B6

Stop bits

Parity

Serial Data Transfer

  • Asynchronous v.s. Synchronous
  • Asynchronous transfer does not require clock signal. However, it transfers extra bits (start bits and stop bits) during data communication
  • Synchronous transfer does not transfer extra bits. However, it requires clock signal

Frame

data

Asynchronous

Data transfer

clk

Synchronous

Data transfer

data

B0

B1

B2

B3

B4

B5

Baud (Baud is # of bits transmitted/sec, including start, stop, data and parity).

slide10

8251

RS232

D[7:0]

TxD

RD

RD

RxD

WR

WR

A0

C/D

TxC

CLK

CLK

RxC

A7

A6

A5

A4

A3

A2

A1

IO/M

8251 USART Interface

slide12

7

6

5

4

3

2

1

0

Mode register

Number of

Stop bits

Baud Rate

Parity enable

0: disable

1: enable

00: Syn. Mode

01: x1 clock

10: x16 clock

11: x64 clock

00: invalid

01: 1 bit

10: 1.5 bits

11: 2 bits

Character length

00: 5 bits

01: 6 bits

10: 7 bits

11: 8 bits

Parity

0: odd

1: even

Programming 8251

  • 8251 mode register
slide13

Programming 8251

  • 8251 command register

EH

IR

RTS

ER

SBRK

RxE

DTR

TxE

command register

TxE: transmit enable

DTR: data terminal ready, DTR pin will be low

RxE: receiver enable

SBPRK: send break character, TxD pin will be low

ER: error reset

RTS: request to send, CTS pin will be low

IR: internal reset

EH: enter hunt mode

slide14

DSR

SYNDET

FE

OE

PE

TxEMPTY

RxRDY

TxRDY

Programming 8251

  • 8251 status register

status register

TxRDY: transmit ready

RxRDY: receiver ready

TxEMPTY: transmitter empty

PE: parity error

OE: overrun error

FE: framing error

SYNDET: sync. character detected

DSR: data set ready

slide15

Read

  • Write

start

start

Check RxRDY

Check TxRDY

No

No

Is it logic 1?

Is it logic 1?

Yes

Yes

Read data register*

Write data register*

end

end

* This clears RxRDY

* This clears TxRDY

Simple Serial I/O Procedures

errors
Errors
  • Parity error: Received data has wrong error -- transmission bit flip due to noise.
  • Framing error: Start and stop bits not in their proper places.
    • This usually results if the receiver is receiving data at the incorrect baud rate.  
  • Overrun error: Data has overrun the internal receiver FIFO buffer.
    • Software is failing to read the data from the FIFO.
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