Understanding the Impacts of 3D Stacked Layouts on ILP Vivek Venkatesan, Manu Awasthi, Rajeev Balasubramonian School of Computing, University of Utah. BACKGROUND. 3D TECHNOLOGY.
Understanding the Impacts of 3D Stacked Layouts on ILP
Vivek Venkatesan, Manu Awasthi, Rajeev Balasubramonian
School of Computing, University of Utah
Interconnects within a processor pipeline are known to be a major bottleneck for performance and power in future processors. Wire delays are Vertical 3D stacking of dies allows reduction of overall wire-lengths and helps alleviate the performance and power overhead of on-chip wiring. The primary disadvantage is that it results in increased power-densities and on-chip temperatures.
Drawback : Increased Thermal Density
Break and Stack
IMPACT OF WIRE DELAYS
3D Folding – Proposed by Puttaswamy et. Al.
Observation : Wire-Delay Limited Architectures stand to benefit more from a 3D integration technology
Proposed Solution : 3D Stacking
Cache Bank (Replicated/Word Interleaved)
Reduced Wire Delays and Better Thermal Density !!
blocks in a processor evaluating each with respect to an
keep heavily communicating blocks closer
closeness in the vertical dimension
2D Performance Comparison
Best Case 3D Performance
3D Technology has the potential to improve processor performance, power and cost
3D wafer bonding traps heat resulting in higher peak and average temperatures
Tiled-architectures with long inter-cluster wires stand to gain more from 3D stacking
Aggressive cooling capabilities may be required to extract the full potential of 3D
Other promising applications of 3D technology include “snap-on” analysis engines, fault-correction engines and stacked memories.