Understanding the Impacts of 3D Stacked Layouts on ILP
This presentation is the property of its rightful owner.
Sponsored Links
1 / 1

Best case 3D (Arch 3/WI) performs 12% better than best case 2D (Replicated Cache banks). PowerPoint PPT Presentation


  • 74 Views
  • Uploaded on
  • Presentation posted in: General

Understanding the Impacts of 3D Stacked Layouts on ILP Vivek Venkatesan, Manu Awasthi, Rajeev Balasubramonian School of Computing, University of Utah. BACKGROUND. 3D TECHNOLOGY.

Download Presentation

Best case 3D (Arch 3/WI) performs 12% better than best case 2D (Replicated Cache banks).

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Best case 3d arch 3 wi performs 12 better than best case 2d replicated cache banks

Understanding the Impacts of 3D Stacked Layouts on ILP

Vivek Venkatesan, Manu Awasthi, Rajeev Balasubramonian

School of Computing, University of Utah

BACKGROUND

3D TECHNOLOGY

Interconnects within a processor pipeline are known to be a major bottleneck for performance and power in future processors. Wire delays are Vertical 3D stacking of dies allows reduction of overall wire-lengths and helps alleviate the performance and power overhead of on-chip wiring. The primary disadvantage is that it results in increased power-densities and on-chip temperatures.

Drawback : Increased Thermal Density

RegFile

Break and Stack

IMPACT OF WIRE DELAYS

3D Folding – Proposed by Puttaswamy et. Al.

  • Wire-latencies predicted to be in 10’s of cycles in future fabrication technologies

  • Studying the impact of wire-delays on performance reinforces the need for interconnect optimization techniques

  • Popular belief: Multi-threading hides wire-delays, not entirely true!

  • Technique to alleviate key wire-delays -> Floor-planning

Observation : Wire-Delay Limited Architectures stand to benefit more from a 3D integration technology

Proposed Solution : 3D Stacking

Cluster

Cache Bank (Replicated/Word Interleaved)

Arch 3

Arch 1

Arch 2

Reduced Wire Delays and Better Thermal Density !!

3D BENEFITS

  • Best case 3D (Arch 3/WI) performs 12% better than best case 2D (Replicated Cache banks).

  • Better thermal profile : Best case (Arch 3/ WI) has just 10 0 C increase from 2D with maximum performance gains

FLOOR-PLANNING

  • Floor-planning generates arbitrary layouts of micro-architectural

    blocks in a processor evaluating each with respect to an

    objective function

  • Include delay-criticality information in the objective function to

    keep heavily communicating blocks closer

  • 3D floor-planning generates 3D layouts, more potential to exploit

    closeness in the vertical dimension

2D Performance Comparison

Best Case 3D Performance

CONCLUSIONS

3D Technology has the potential to improve processor performance, power and cost

3D wafer bonding traps heat resulting in higher peak and average temperatures

Tiled-architectures with long inter-cluster wires stand to gain more from 3D stacking

Aggressive cooling capabilities may be required to extract the full potential of 3D

Other promising applications of 3D technology include “snap-on” analysis engines, fault-correction engines and stacked memories.


  • Login