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TMS320C24x Overview

TMS320C24x Overview. Max Chyou Engineering Manager AmRoad Co.Ltd. Maxchyou@amroad.com.tw. Contents. Introduction Architectural Overview Clocks Power Management Interrupts Timer PWM Architecture Space Vector Q&A. Introduction. Introduction. Why DSP? Benefits of Digital System

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TMS320C24x Overview

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  1. TMS320C24x Overview Max Chyou Engineering Manager AmRoad Co.Ltd. Maxchyou@amroad.com.tw

  2. Contents • Introduction • Architectural Overview • Clocks • Power Management • Interrupts • Timer • PWM Architecture • Space Vector • Q&A

  3. Introduction

  4. Introduction Why DSP? • Benefits of Digital System • Reliability, flexibility • Time sharing / task switching • Freedom from environmental effects • Bandwidth and resolution of analog system

  5. Introduction Why DSP? • Optimized Architecture • Instruction set tailored for signal processing functions • Architecture minimizes numerical problems in processing discrete signals

  6. Introduction Why DSP? • High Performance • Implementation of complex algorithms in real-time • Implementation of high sampling rates • Minimizes computational delay • Performance to implement multiple functions

  7. Features Single-cycle instruction DSP instruction set Multiple buses Hardware multiplier Hardware scaling shifters Benefits High sampling rates / control of high bandwidth system Real-time execution of advanced control algorithms Simultaneous access of data and instructions Minimize computational delays Introduction

  8. Features Hardware scaling shifters 16-bit word length 32-bit ALU / ACC Hardware stack Saturation mode Benefits Fast scaling / dynamic range Minimize quantization errors Minimize truncation errors Fast interrupt processing Prevent wrap around of ACC Introduction

  9. Function Notch filter algorithms Adaptive Kalman filter algorithms State estimator algorithms Vector control algorithms Pulse width modulation (PWM) Benefits Cancel mechanical resonance Reduce sensor noise Estimate multiple variables Real-time axis transformation Improve motor control Introduction

  10. Function Notch filter algorithms Adaptive Kalman filter algorithms State estimator algorithms Vector control algorithms Pulse width modulation (PWM) Benefits Cancel mechanical resonance Reduce sensor noise Estimate multiple variables Real-time axis transformation Improve motor control Introduction

  11. Function High order PID control loop High sample rate Time division multiplexing Fuzzy set control algorithms Benefits Precise control High system bandwidth Several control system implementations with 1 DSP device “Intelligent” control Introduction

  12. Function Dead band controller State controller Power factor correction FFT algorithms Adaptive control algorithms Benefits Quick settling time Control many variables Reduce motor power loss Analyze mechanical resonance Reduce disturbance effects Introduction

  13. DSP CORE

  14. Core Architecture Program Bus • Program Memory Controller Memory Mapped Registers A(15-0) • D(15-0) Data Bus * ‘C240 Only System Interface Module * Data Memory Multiplier Peripherals ALU/Shifters Peripherals (Event Mgr)

  15. Core Architecture 16 Data Bus 16 16 16 16 T (16) MUX MULTIPLIER 16 16 P (32) SHIFTER (0-16) 32 SHIFTER (-6, 0, 1, 4) 32 32 MUX 32 32 ALU (32) 32 C ACCH (16) ACCL (16) • 32 SFL (0-7) Data Bus 16

  16. Core Architecture 16 Program Bus MUX 16 16 PC 16 16 • • 16 12-15 STACK Address (8x16) Program ROM / FLASH 16 A(15-0) • MUX Instruction 16 16 16 D(15-0) MUX 16 16 Data Bus To Data Memory

  17. Peripheral

  18. 39.0625 kHz Prescaler Watchdog ADC Prescaler CPU Core Memory CAN Event Manager SCI SPI External Memory Interface Clock Signals XTAL1 x4 PLL Clock Module WDCLK crystal CLKOUT XTAL2 CPUCLK ADCCLK

  19. Architecture Data Bus Program Bus 16 16 AR0(16) From Program Memory 9 AR1(16) 3 7 LSB From IR AR2(16) 3 DP(9) ARP(3) AR3(16) 9 AR4(16) 16 16 16 3 AR5(16) 16 MUX AR6(16) 16 • AR7(16) ARB(3) • • 16 MUX ARAU(16) MUX 3 16 16 Data / Program RAM Data RAM 16 MUX 16 16 16

  20. GP Timers Watchdog Timer Compare Unit SPI PWM Outputs SCI Dead-Band Logic A/D Converter Capture Unit I /O Pins Quadrature Encoder Pulse (QEP) CAN Architecture Event Manager Data Bus Non-EV Manager System Interface Module (‘F/C240 only)

  21. Watchdog Timer /64 111 6 - Bit Free - Running Counter /32 110 WDPS /16 101 • /8 100 WDCR . 2 - 0 WDCLK • 011 /4 010 /2 System Reset WDCR . 6 • 001 CLR WDDIS 000 • • WDCNTR . 7 - 0 8 - Bit Watchdog Counter One-Cycle Delay CLR • WDCR . 5 - 3 WDCHK 2-0 Watchdog Reset Key Register 55 + AA Detector Good Key • • 3 / • • Bad Key / Bad WDCR Key 3 1 0 1

  22. Power Manager Low Power Mode Normal Run Idle 1 Idle 2 Halt Comments CPU off All Peripherals off (except watchdog) Oscillator & Watchdog off Power ~80 mA @ 20 MIPS ~ 50 mA ~ 7 mA ~ < 1 mA Note: PLL is on all the time for ‘X241/2/3!

  23. Interrupt RS • 2 non-maskable interrupts (RS, NMI) • 6 maskable interrupts (INT1 - INT6) NMI INT1 ‘C24x CORE INT2 INT3 INT4 INT5 INT6

  24. To RS pin RS pin active System Reset ‘C24x Core Watchdog Timer RS

  25. RS RS 17 CPUCLK cycles Reset Vector Fetched 8 cycles min. Reset Vcc External Device ‘C24x 10K • • reset • RS pin must be held low a minimum of one CPUCLK • cycle to ensure recognition of a reset • Once a reset source is activated, RS pin is driven low • for 8 CPUCLK cycles minimum

  26. RS RS PDPINT XINT1 XINT2 NMI Event Management EV and Non-EV Peripherals ‘C24x CORE Internal Sources External Sources NMI INT1 INT2 EV and Non-EV Peripheral Interface INT3 INT4 INT5 INT6

  27. INT1 INT2 INT3 Event Management Core Interrupt (IFR) “Latch” (IMR) “Switch” (INTM) “Global Switch” 1 ‘C24x Core 0 1

  28. Arbitrator Event Management To Core Interrupt INT1 XINT1 Flag Polarity Enable XINT2 Flag Polarity Enable ADCINT Flag Enable

  29. Event Management Core Compare 1,2,3 Timer 1 INT1 INT2 INT3 INT4 INT5 INT6 Timer 2 EV Capture 1,2,3 PDPINT • XINT1,2 (high priority) SPI, SCI, CAN (high priority) ADC (high priority) Non EV SPI, SCI, CAN (low priority) ADC (low priority) XINT1,2 (low priority)

  30. Latency • Latency • delay between an interrupt request and the first interrupt specific code fetch • TMS320C24x Latency Components • Peripheral interface time (synchronization) • CPU response time (core latency) • ISR branching time (ISR latency)

  31. INTCALL POPD RET PSHD Stack Operation • Hardware stack is expandable to data memory using PSHD/POPD 8-LEVEL HARDWARE STACK PC DATAMEMORY PUSH POP ACCL

  32. Protection • Interrupt latency may not protect hardware when responding to over current through ISR software • PDPINT has a fast, clock independent logic path to high-impedance the PWM output pins (~ 45-55 ns) ‘C24x DSP CORE P W M O U T P U T S PDPINT flag clock synch. Over Current Sensor PDPINT Enable

  33. Timer GP Timer Stop/Hold Up Counting Up/Down Counting Continuous Continuous Directional

  34. Timer Architecture TMRCLK pin CPUCLK (internal DSP) MUX TxCNT Timer Counter Compare Logic Prescale Counters clocking signal 16 TMRDIR pin 16 Period Register Buffer TxPR Period Register auto-load on underflow

  35. UP Timer This example: TxPR = 3 (initially) Prescale = 1 CPU writes a 2 to period reg. buffer anytime here TxPR=2 is auto-loaded on underflow here 3 3 2 2 2 2 1 1 1 1 0 0 0 0 TxCNT Reg. TxCON[6] CPUCLK

  36. U/D Timer • Seamless up/down repetition • Up/down count period is 2*TxPR This example: TxPR = 3 (initially) Prescale = 1 CPU writes a 2 to period reg. buffer anytime here TxPR=2 is auto-loaded on underflow here 3 2 2 2 2 1 1 1 1 1 1 0 0 0 0 TxCNT Reg. TxCON[6] CPUCLK

  37. GP Timer 2 Compare Full Compare 1 GP Timer 1 Compare GP Timer 2 Full Compare 2 GP Timer 1 QEP Circuit Full Compare 3 PWM Architecture Reset INT2, 3, 4 2 TMRCLK / TMRDIR / EV Control Registers / Logic ADC Start Output Logic Waveform Generator T1PWM/T1CMP • PWM1/CMP1 PWM Circuits Output Logic PWM2/CMP2 PWM3/CMP3 PWM Circuits Output Logic PWM4/CMP4 PWM5/CMP5 PWM Circuits Output Logic PWM6/CMP6 Waveform Generator Output Logic T2PWM/T2CMP CLK Data Bus MUX DIR • CAP1/QEP1 Capture Units • CAP2/QEP2 CAP3

  38. 3 3 3 3 2 2 1 1 0 0 0 0 0 0 0 TIMER This example: TxPR = 3 Prescale = 1 CPUCLK as source Count holds at TxPR=3 since TMRDIR = hi on rising clock edge 2 CPUCLK latency 2 CPUCLK latency TxCNT Reg. TMRDIR TxCON[6] CPUCLK

  39. PWM Architecture This example: TxCON.3-2 = 00 (reload TxCMP on underflow) TxPR = 3 TxCMP = 1 (initially) Prescale = 1 CPU writes a 2 to compare reg. buffer anytime here TxCMP=2 is loaded here 3 3 3 2 2 2 1 1 1 0 0 0 0 TxCNT Reg. TxPWM/TxCMP (active high) TxCINT CPUCLK

  40. PWM Architecture This example: TxCON.3-2 = 01 (reload TxCMP when on underflow or period match) TxPR = 3 TxCMP = 1 (initially) Prescale = 1 TxCMP loads with a 1 TxCMP loads with a 2 TxCMP loads with a 1 3 3 2 2 2 2 1 1 1 1 0 0 0 TxCNT Reg. TxPWM/TxCMP (active high) CPUCLK

  41. PWM Architecture SV Compare Logic Dead Band 16 T1CNT (GP Timer 1) MUX sym. asym. 16 Output Logic PWMy/ CMPy Compare Reg. Buffer CMPRx compare register auto-load on software selectable events

  42. Space Vector

  43. V s V V V a c b DTPH3 DTPH1 DTPH2 Space Vector Only states of transistors 1, 3, & 5 need be determined since 2, 4, & 6 are their respective compliments Switching State Notation: (Q5,Q3,Q1) e.g. (0,0,1) means gate 1 is on, gates 3 & 5 are off 3 5 1 DTPH1 DTPH2 DTPH3 4 6 2 GND 3-Phase Power Converter

  44. V c i/2 i 60° y V a x 60° i/2 V b Space Vector (Q5,Q3,Q1) = (001)  Va=Vs , Vb=Vc= GND Vs /3 2Vs /3 Vs /3 Vs /3 Y-Connected Motor Windings Showing Current Flow Voltage Drop Vectors

  45. Space Vector U120 (010) U60 (011) O(000) U180 (110) U0 (001) O(111) U240 (100) U300 (101) Basic Space Vectors w/ Switching Patterns

  46. U60 (011) Uout T 2 U0 (001) T 1 Space Vector • Approximate desired voltage drop vector as a linear combination of the basic space vectors • Coefficients are duration times

  47. Space Vector T1PR match Full compare #2 match GP Timer 1 value Full compare #1 match DTPH1 DTPH2 DTPH3 T2/2 T1/2 Tp/2 U0 (001) U60 (011) O (111) O (111) U60 (011) U0 (001)

  48. PWM supply rail Gate Signals are Complimentary PWM to motor phase • Transistor gates turn on faster than they shut off • Short circuit if both gates are on at same time!

  49. DTPHx_ Asymmetric PWM Example CPUCLK (20 MHz) Clock prescaler PHx edge detect PHx ENA Counter 8-bit DT reset Comparator DTPHx DT 4-bit period (DBTCON.11-8) dead time DTPHx DTPHx_

  50. A/D Converter 2-Level FIFO Sample & Hold 10 bit A/D Converter 8/1 MUX Ch. 0-7 2-Level FIFO VREFHI Control & Reference Circuitry VREFLO ADCSOC Internal Data Bus VCCA 5 volts AGND GND Event Manager SOC Signal

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