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Testing for Designed Board

Testing for Designed Board. 1.1 Customer Concept. sampling frequency : 138.24MHz / Interpolation : 4x Enable Digital Mixer fs /2 Disable NCO. FPGA 138.24MSPS DATA. ADC. DAC3484. 241.92MHz. 241.92MHz. 1.2 Test Result. [DAC3484 Register]. 1.3 Question. -- Why signal is break ?

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Testing for Designed Board

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  1. Testing for Designed Board

  2. 1.1 Customer Concept • sampling frequency : 138.24MHz / Interpolation : 4x • EnableDigital Mixer fs/2 • Disable NCO FPGA 138.24MSPS DATA ADC DAC3484 241.92MHz 241.92MHz

  3. 1.2 Test Result [DAC3484 Register] 1.3 Question -- Why signal is break ? -- Center Freq is not 241.92MHz. Why?

  4. Testing for TSW1400 + DAC3484 EVM

  5. 1. Test Configuration Signal Generator Spectrum TSW1400 DAC34H84EVM PC

  6. 3. Test Result - Signal source file: single tone - F sampling frequency : 307.2MHz / Interpolation : 4x [TSW1400] [DAC3484] [DAC34H84 Register] [Spectrum] Test Result : Normal

  7. 3. Test Result - Signal source file: WCDMA_TM1_complexIF30MHz_Fdata307.2MHz_1000 - F sampling frequency : 307.2MHz / Interpolation : 4x [TSW1400] [DAC3484] [DAC34H84 Register] [Spectrum] Test Result : Normal

  8. 3. Test Result - Signal source file: WCDMA_TM1_complexIF30MHz_Fdata307.2MHz_1000 - F sampling frequency : 307.2MHz / Interpolation : 2x [TSW1400] [DAC3484] [DAC34H84 Register] [Spectrum] Test Result : Normal

  9. 3. Test Result - Signal source file: single tone - F sampling frequency : 138.24MHz / Interpolation : 4x [TSW1400] [DAC3484] PLL unlock [DAC34H84 Register] [Spectrum] Test Result : Abnormal Signal unstable Center Freq mismatch

  10. 3. Test Result - Signal source file: single tone - F sampling frequency : 138.24MHz / Interpolation : 2x [TSW1400] [DAC3484] PLL unlock [DAC34H84 Register] [Spectrum] Test Result : Abnormal Signal unstable Center Freq mismatch

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