A Wide-Input-Range 8 bit Cyclic TDC. Reportor : Zhu kunkun. INTRODUCTION.
Reportor : Zhu kunkun
TDC (time to digital converter) is widely used in many applications, such as the phase or frequency detection of DPLL / APLL [1, 2]. In recently researches, TDC can be used in time domain ADC Combining with the VTC (voltage to time) [3-6]. The gigasample rate TDC has been released in , the combination of series and parallel delay lines are used. However, the resolution is unsatisfactory and the performance has to be calibrated by DAC on chip. Two-step TDC architecture mentioned in the , coarse and fine conversions achieve a large range in a way, however, the main issue is that the minimum input pulse duration limited the performance. In , cyclic pulse-shrinking TDC with attenuators is used to the temperature sensor. Large stages attenuators including inhomogeneity of the gates occupy many chip area and the conversion rate is very low. A cyclic TDC which similar to cyclic ADC had been mentioned in , the narrow input range is limited this type TDC applied in time domain ADC.
As the important element of the cyclic TDC is TDA (time difference amplifier). The TDA can increase the resolution of a time to digital converter (TDC) and enlarge the dynamic input range and gain of time measurement circuits. The TDAs based on S-R latch [9, 10], however, suffer from a limited input range and low linearity range. The cross coupled delay chains TDAs [11, 12] have low gain and the linearity limited by the mismatch due to utilizing lots of delay units. If an extra feedback circuits can’t to be used, the gain would be very difficult to control. To increasing the input range and stabilizing the gain, calibration circuits have been adopted, however, additional calibration of TDA in the chip level will increase the chip area and circuits complexity.