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ABET EC2000 Criterion 3 Outcomes a thru k Assessment

EECS 1100 Digital Logic Design A Presentation by G. Serpen. ABET EC2000 Criterion 3 Outcomes a thru k Assessment. EECS 1100 Digital Logic Design. Catalog Description: EECS - 1100  Digital Logic Design [4 hours] Number representation and Boolean Algebra.

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ABET EC2000 Criterion 3 Outcomes a thru k Assessment

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  1. EECS 1100 Digital Logic Design A Presentation by G. Serpen ABET EC2000 Criterion 3 Outcomes a thru k Assessment

  2. EECS 1100 Digital Logic Design • Catalog Description: EECS - 1100  Digital Logic Design [4 hours] • Number representation and Boolean Algebra. • Combinational circuit analysis and design. • K-map and tabulation methods. • Multiplexers, decoders, adders/subtracters and PLD devices. • Sequential circuit analysis and design. • Registers, counters and recognizers. • 3 hours lecture and one 2- 1/2 hour laboratory session.

  3. EECS 1100 ABET ASSESSMENT ABET Outcome Student Learning Objectives The student will be able to conduct (or simulate) an experiment to learn the logic design and prototyping process in order to acquire requisite hands-on skills and report the results through a well-defined and formatted written document. develop a computer simulation to correlate or interpret experimental results. list and discuss several possible reasons for deviations between predicted and measured results from an experiment, choose the most likely reason and justify the choice, and formulate a method to validate the explanation. • Outcome 3b (design and conduct experiments, analyze and interpret data)

  4. EECS 1100 ABET ASSESSMENT ABET OUTCOME STUDENT LEARNING OBJECTIVES The student will be able to design a digital module with combinational and sequential logic components to be able to address any problem in the applicable domain and report the results in a typical engineering design document. build a prototype of a digital logic circuit and demonstrate that it meets performance specifications, which are limited to functional correctness and resource minimization, i.e. minimal product-of-sums or sum-of-products only for combinational design only. list and discuss several possible reasons for deviations between predicted and measured results from an experiment or design, choose the most likely reason and justify the choice, and formulate a method to validate the explanation. • Outcome 3c (design a system, component, or process)

  5. EECS 1100 ABET ASSESSMENT ABET outcome Student learning objectiveS The student will be able to write an effective technical (experiment) report for lab experiments. • Outcome 3g (communicate effectively)

  6. EECS 1100 ABET ASSESSMENT Abet outcome Student learning objectiveS The student will be able to Use state-of-the-art combinational and sequential logic design methodologies, techniques, and paradigms. Use computer-aided analysis and design software to develop logic circuits and simulate them. Use tools including a scope, and a logic analyzer to prototype, debug and test a combinational and sequential logic circuit at the gate level utilizing the MSI/LSI technology. Use online resources to obtain current literature on engineering components, devices and systems. • Outcome 3k (Use modern engineering techniques, skills, and tools)

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