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SEU-Hardened Storage Devices in a 0.15 µm Antifuse FPGA – RTAX-S. J. J. Wang 1 , B. Cronquist 1 , J. McCollum 1 , R. Gorgis 1 , R. Katz 2 , and I. Kleyner 3 1 Actel Corporation 2 NASA Office of Logic Design 3 Orbital Science, Greenbelt, MD20771. Abstract.

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seu hardened storage devices in a 0 15 m antifuse fpga rtax s
SEU-Hardened Storage Devices in a 0.15 µm Antifuse FPGA – RTAX-S

J. J. Wang1, B. Cronquist1, J. McCollum1, R. Gorgis1, R. Katz2, and I. Kleyner3

1 Actel Corporation2 NASA Office of Logic Design3 Orbital Science, Greenbelt, MD20771

abstract
Abstract

The storage devices in the RTAX-S family are SEU-hardened. The flip-flop is hardened by hard-wired triple module redundancy, and the RAM is hardened by software error-correcting code (ECC), which is a shortened Hamming code.

These hardened storage devices are tested by heavy ion beam, and their SEU cross sections are extracted from test data for rate predictions in a typical environment. Final results show that both devices are hardened effectively, and the measured upset errors are due to SET and noise.

tmr flip flop heavy ion beam test
TMR Flip-Flop Heavy Ion Beam Test
  • Device under test:
    • RTAX2000-S
    • Four pre-production devices
  • Logic design:
    • Two 100-bit shift registers, SH1 and SH2, for SEU measurement
    • Two user-level TMR shift registers for noise monitoring
    • Checkerboard pattern running at 2 MHz during irradiation
    • -10% VCC for SEU measurement, +10% VCC for SEL and SEDR
  • Heavy ion beam:
    • BNL Tandem Van de Graaff
    • Cl-35, Ni-58, Br-81, I-127
    • Effective LET=37.5 to 104 MeV•cm2/mg
tmr flip flop seu rate prediction
TMR Flip-Flop SEU Rate Prediction
  • Use Space Radiation 4.5 simulator:
    • Weibull parameters: LET0=10MeV•cm2/mg, width=35MeV•cm2/mg, shape=2, saturation cross-section=9x10-10cm2
    • Active volume: depth=0.15µm, funnel depth=0.3µm
    • Environment: GEO solar minimum
    • Shielding: 100mil Aluminum
  • Upsets Rate:
    • 1.96x10-11 upsets/bit•day
    • Based on RTSX-S experiences, the measured upsets are probably due to SET and testing noise
edac ram in rtax s
EDAC-RAM in RTAX-S
  • ECC:
    • Shortened Hamming code to detect 2 errors and correct 1 error
    • S. Lin and D. J. Cosello, Jr., “Error Control Coding: Fundamentals and Applications,” Prentice Hall, New Jersey, 1983
    • http://www.actel.com/documents/EDAC_AN.pdf “Using EDAC RAM for RadTolerant RTAX-S FPGAs and Axcelerator FPGAs”
  • Scrubbing:
    • Reduce SEU rate for long-term storage
    • User selects the scrubbing rate
  • Word width:
edac ram heavy ion beam test
EDAC-RAM Heavy Ion Beam Test
  • Test logic designed by ACTgen macro
  • Beam test uses very high fluxes (1x104-1x105 Ions/cm2/sec)
  • Have to turn on scrubbing during irradiation
  • Test ports not used
  • ECC and scrubbing are tested simultaneously because scrubbing alone cannot reduce SEU
edac ram seu rate prediction
EDAC-RAM SEU Rate Prediction
  • Use Space Radiation 4.5 simulator:
    • Weibull parameters: LET0=30MeV•cm2/mg, width=10MeV•cm2/mg, shape=1.5, saturation cross-section=3.91x10-9cm2
    • Active volume: depth=0.15µm, funnel depth=0.3µm
    • Environment: GEO solar minimum
    • Shielding: 100mil Aluminum
  • Upsets Rate Boundary:
    • 8-bit word is < 2.55x10-11 upsets/word•day
    • 16-bit word is < 1.57x10-10 upsets/word•day
    • 32-bit word is < 4.18x10-10 upsets/word•day
scrubbing rate dependence
Scrubbing Rate Dependence
  • Predicted upsets derived from single-bit-upset cross section and probability theory
  • Prediction and Experiment match at high upsets but not at low upsets
  • Low upsets in Experiment may be due to SET and noise
conclusions
Conclusions
  • Hard-wired TMR flip-flop is radiation hard.
  • The measured upset errors in hardened flip-flops are probably due to SET and noise.
  • EDAC-RAM is radiation hard, which means the ECC scheme and scrubbing are performing as expected.
  • Low level upsets measured in EDAC-RAM are probably due to SET and noise.
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