Ece 353 introduction to microprocessor systems
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ECE 353 Introduction to Microprocessor Systems. Michael G. Morrow, P.E. Week 11. Topics. Interrupt Concepts ARM7TDMI Interrupt Handling ADuC7026 Interrupt Implementation Interrupt Sources Interrupt Service Routines (ISRs) Interrupt Driven Systems Software Interrupts and Exceptions

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ECE 353 Introduction to Microprocessor Systems

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Ece 353 introduction to microprocessor systems

ECE 353Introduction to Microprocessor Systems

Michael G. Morrow, P.E.

Week 11


Topics

Topics

  • Interrupt Concepts

  • ARM7TDMI Interrupt Handling

  • ADuC7026 Interrupt Implementation

    • Interrupt Sources

  • Interrupt Service Routines (ISRs)

  • Interrupt Driven Systems

  • Software Interrupts and Exceptions

  • Interrupt Priority and Latency

  • Debugging Interrupt Hardware and Software


Why use interrupts

Why Use Interrupts?

  • Maximize processor utilization and efficiency

  • Allow use of sleep/idle states to save power

  • Minimize latency in responding to complex input/output structures

  • Facilitate event-driven applications and preemptive multitasking


Interrupt primer

Interrupt Primer

  • Terminology

  • Basic interrupt hardware

    • Interrupt request

    • Interrupt acknowledge

    • Interrupt masking

      • Non-maskable interrupt (NMI)

    • Interrupt sensitivity

      • Level-sensitive

      • Edge-sensitive


Interrupt concepts

Interrupt Concepts

  • Supporting multiple interrupt sources

    • Polled interrupts

    • Vectored interrupts

      • Fixed ISR locations

      • Vector table implementations

    • Generic implementation

  • Prioritization Schemes

    • Fixed

    • Rotating

    • Hierarchical

  • Software interrupts and exceptions


Arm7tdmi interrupt handling

ARM7TDMI Interrupt Handling

  • Interrupt modes

    • IRQ

      • Banks R13, R14, SPSR

    • FIQ

      • Banks R8-R12, R13, R14, SPSR

    • SWI (software interrupt) discussed later

  • Interrupt control

    • CPSR I/F flags

  • Interrupt processing sequence

  • Interrupt nesting


  • Aduc7026 hardware interrupts

    ADuC7026 Hardware Interrupts

    • Interrupt sources

      • Internal peripherals

      • External IRQ pins

      • Programmed interrupts

    • Interrupt sources can be individually programmed to generate either FIQ or IRQ mode entry.

      • No prioritization of individual sources at a given level (FIQ/IRQ)


    Aduc7026 interrupt mmrs

    ADuC7026 Interrupt MMRs

    • These MMRs are used to control the interrupt handling

      • IRQSIG, FIQSIG

        • Ones indicate that the source has an interrupt pending

      • IRQEN, FIQEN

        • Ones indicate that the interrupt request from the source is unmasked (i.e. the interrupt source is enabled)

      • IRQSTA, FIQSTA

        • Ones indicate that the sources have an interrupt enabled and pending

        • Used in ISR to determine which device(s) need(s) service

      • IRQCLR, FIQCLR

        • Write ones to clear the corresponding bit in IRQEN, FIQEN (i.e. to mask an interrupt source)

        • This is NOT how you clear an interrupt request in the ISR!


    Aduc7026 programmed interrupts

    ADuC7026 Programmed Interrupts

    • The programmed interrupt feature allows us to programmatically force an entry into FIQ mode or IRQ mode

      • Write to SWICFG register, do not need to have programmed interrupt enabled in IRQEN/FIQEN

      • Note that the use of “SWI” has absolutely nothing to do with the ARM7 SWI instruction and supervisor mode


    Interrupt service routines

    Interrupt Service Routines

    • ISR prerequisites

      • aduc7026.s

    • ISR implementation

      • Context save

      • Clear IRQ from interrupt source

      • Allow nesting (if desired)

      • Handle interrupt

      • Context restore

      • Return from interrupt/exception

    • Interrupt Checklist on course web page

    • Shared subroutines and resources


    Interrupt driven systems

    Interrupt Driven Systems

    • Foreground vs. background tasks.

    • Events determine the actual order of execution.


    Software interrupts exceptions

    Software Interrupts & Exceptions

    • SWI instruction

    • Exceptions

      • ARM7TDMI exceptions

        • Prefetch abort

        • Data abort

        • Undefined instruction

        • Reset

      • Other common exceptions

        • Divide error

        • Single-step

        • Breakpoint


    Interrupt prioritization and latency

    Interrupt Prioritization and Latency

    • Handling multiple simultaneous interrupts and exceptions

      • ARM7TDMI exception priorities

      • Interrupt prioritization schemes

        • Fixed

        • Rotating

        • Tiered (hierarchical)

    • Interrupt Latency

      • Definition

      • ADuC7026 latency specifics


    Interrupt issues

    Interrupt Issues

    • Using periodic interrupts to perform iterative tasks

    • What to do when good interrupts go bad…

      • Software debugging

      • Hardware debugging

      • Real-time issues

      • Inter-process communication (IPC) issues


    In class assessment quiz

    In-Class Assessment Quiz

    • What sort of safeguards might you need to design into NMI hardware?

    • For the ARM7TDMI, describe what happens between an IRQ being asserted and the actual execution of the ISR.

    • What are the differences between vectored interrupts and polled interrupts?


    In class assessment quiz1

    In-Class Assessment Quiz

    • What is a ‘level-sensitive’ interrupt?

    • What problems could arise when using a semaphore to control access to a resource used by the main program and an ISR? What ARM7TDMI instruction(s) help handle this issue?

    • Draw a flowchart for a periodic (1 KHz) ISR that will be used to generate precise millisecond delays. Only a single word variable is to be used to communicate with the ISR.


    Wrapping up

    Wrapping Up

    • Homework #6 due Wednesday, 4/25.

    • Reading for next week

      • Textbook 15

      • Supplement #5 ([email protected])


    Arm7 cpsr

    ARM7 CPSR

    • Current Process Status Register (CPSR)

      • Condition code flags (N, Z, C, V)

      • Interrupt disable bits (I, F)

      • Thumb mode enable (T)

        • Never change directly!

      • Mode select

        • These bits cannot be changed in User mode


    Arm7 spsr

    ARM7 SPSR

    • Suspended Process Status Register (SPSR)

      • SPSR is only present when the CPU is operating in one of the exception modes

        • Each exception mode has its own SPSR, since exception handlers may cause other exceptions.

      • SPSR is a copy of the CPSR immediately before the exception mode was entered.

        • When returning from the exception, the value in SPSR is used to restore the CPSR to the proper state for the process that was interrupted.


    Arm7 register banking

    ARM7 Register Banking


    Interrupt example hardware

    Interrupt Example - Hardware


    Aduc7026 s

    AREA Reset, CODE, READONLY

    ARM

    ; Exception Vectors mapped to Address 0.

    ; Absolute addressing mode must be used.

    Vectors

    LDR PC, Reset_Addr

    LDR PC, Undef_Addr

    LDR PC, SWI_Addr

    LDR PC, PAbt_Addr

    LDR PC, DAbt_Addr

    NOP ; Reserved Vector

    LDR PC, IRQ_Addr

    LDR PC, FIQ_Addr

    Reset_Addr DCD Reset_Handler

    Undef_Addr DCD Undef_Handler

    SWI_Addr DCD SWI_Handler

    PAbt_Addr DCD PAbt_Handler

    DAbt_Addr DCD DAbt_Handler

    IRQ_Addr DCD IRQ_Handler

    FIQ_Addr DCD FIQ_Handler

    Reset_Handler

    ;setup PLL and power control

    LDR R1, =PLL_MMR_BASE

    aduc7026.s


    Aduc7026 s1

    aduc7026.s

    LDR R0, =Stack_Top

    ; Enter Undefined Instruction Mode and set its Stack Pointer

    MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit

    MOV SP, R0

    SUB R0, R0, #UND_Stack_Size

    ...

    ; Enter FIQ Mode and set its Stack Pointer

    MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit

    MOV SP, R0

    SUB R0, R0, #FIQ_Stack_Size

    ; Enter IRQ Mode and set its Stack Pointer

    MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit

    MOV SP, R0

    SUB R0, R0, #IRQ_Stack_Size

    ; Enter Supervisor Mode and set its Stack Pointer

    MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit

    MOV SP, R0

    SUB R0, R0, #SVC_Stack_Size

    ; Enter User Mode and set its Stack Pointer

    MSR CPSR_c, #Mode_USR

    MOV SP, R0

    SUB SL, SP, #USR_Stack_Size

    ; jump to user code

    B __main


    Aduc7026 interrupt latency

    ADuC7026Interrupt Latency


    Aduc7026 exception priority

    ADuC7026Exception Priority


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