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Digital Receiver G. Comoretto, A. Russo, G. Tuccari, A Baudry, P. Camino, B. Quertier Dwingeloo, February 27, 2009. FP7 Uniboard project. Framework. Wideband radioastronomy receivers Instantaneous BW 4-12 GHz Digitizers: current 1-2 GHz, near future 4-8 GHz

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slide1
Digital Receiver

G. Comoretto, A. Russo, G. Tuccari,

A Baudry, P. Camino, B. Quertier

Dwingeloo, February 27, 2009

FP7 Uniboard project
framework
Framework
  • Wideband radioastronomy receivers
    • Instantaneous BW 4-12 GHz
    • Digitizers: current 1-2 GHz, near future 4-8 GHz
  • Digital hardware: limited by clock, 100-300 MHz bandwidth

→ Need for frequency multiplexing

  • Multibeam receivers
    • Tens → hundreds of pixels

7 feed FP5 Faraday receiver

existing systems
Existing systems

DBBC

  • DBBC
    • 4x 1GHz BW, up to 16 Virtex5 cores
    • EVN standard: 4 cores = VLBI terminal
    • DBBC3: wider band ADC3 & V.6 core
  • MPI-Agilent FFT Spectrometer
    • 1 GHz BW, Virtex4 core
    • Up to 8 boards on a PCI bus
  • Casper
    • Up to 1.5 GHz BW, 1x (IBOB) or 5 x Virtex2 (BEE2)
    • ROACH: Virtex-5 based

Avoid duplications!

Keep an open path to future apps & HW

ROACH

specifications
Specifications
  • Input:
    • Bandwidth: 4 GHz (8 GS/s)
    • Quantization: 6 bit minimum (8 bit possible)
    • Future development, 2-3 yrs: 8 GHz 4-6 bit
    • Format: data on several 10G links, one sample per link, time multiplexed
  • Output:
    • Bandwidth: up to 64 MHz/channel (128 MS/s), up to 64 channels
    • Quantization: 1, 2, 4, 8 bit
    • Format: Standard MK5C format, UDP packets, on 10G links
  • Each channel position and BW independently selectable (with limitations)
  • Everything fits in a single board
general structure
General structure
  • Two stage filter
  • 1st stage:
    • Polyphase FFT
    • real input
    • 32x250MHz complex output, divided into 8 groups
    • 125 MHz channel spacing
  • 2nd stage:
    • Tunable filter: LO/mixer, low-pass FIR, complex-to-real
    • 4 sets of 16 FIRs
    • Each set selects input among a 1st stage channel group
high sfdr using polyphase filter
High SFDR using polyphase filter
  • 8 GHz BW likely affected by RFI
  • RFI mitigation by excision of affected spectral region
  • Good chan.-to-chan. rejection to avoid contamination
  • 18 bit multipliers: limit to ~85 dB SFDR
  • Filter design: 85 dB stopband
  • 96% useful BW, 0.04 dB ripple
  • >90 dB with 94% BW

channel 1

channel 2

channel 3

Out BW

Channels overlapped to avoid holes

how to fit in the uniboard
How to fit in the Uniboard
  • Uniboard structure:
  • 4 input + 4 output FPGAs
  • Each FPGA has 2x10G in/out
  • No vertical interconnect
  • 4x4 fixed interconnect between input and output FPGAs
  • 2.5 Gbps per link
    • 250 MS/s @ 8 bit
2 stage dit fft
2 stage DIT FFT
  • Decimation in time FFT algorithm:
    • separate data flow for parallel decimated samples
  • Limitation in interconnections: only selected channels processed
channels and groups
Channels and groups

32 overlapping channels

½ channel spacing

Channels are grouped in groups of 4

Groups 0, 1, 2, 3

Groups 4, 5, 6, 7

Up to 4 groups available at each time:

segmented coverage of whole 4 GHz (with edge holes, ~4% lost)

or continuous coverage of narrower band

8 bit between stages enough
8 bit between stages enough?
  • Limited BW between input and output FPGAs: max 256MS @ 8 bit per link
  • Requantization with 8 bit may degrade SFDR
  • Tests with Gaussian noise + spectral line in 1 channel
  • > 80 dB SFDR observed
2 nd stage fir
2nd stage FIR
  • Derived from ALMA Tunable Filterbank
  • Variable Decimation FIR Filter: D=2-256
    • Taps: 32*D, tap recirculation, symmetric
    • 32 (2x16, real-imaginary) multipliers

Output conversion to real by ½ band shift

Specifications TBD.

    • Example from ALMA design
    • 18 bit required for high rejection
    • Tradeoff between complexity and performances

Example: filter performance for 9 bit, 94% BW, 16 multipliers

½ to 1/256 BW

conclusions
Conclusions
  • 4 GHz BW, 64 tunable channels system feasible in a single Uniboard
  • 4x1GHz bypassing 2nd butterfly (but easier w. DBBC!)
  • 8 GHz BW feasible (Phase 2 of the project)
  • >80 dB spurious free dynamic range (may improve)
  • Applications
    • Front-end for other systems
    • VLBI channelization system
    • FFT very wide band spectrometer (e.g. 4GHz 64k pts)
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