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Computer Architecture

Computer Architecture. Pipelining Basics. Sequential Processing. Pipelined Processing. Basic Steps of Execution. 1. Instruction fetch step (IF) 2. Instruction decode/register fetch step (ID) 3. Execution/effective address step (EX) 4. Memory access (MEM) 5. Register write-back step (WB).

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Computer Architecture

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  1. Computer Architecture Pipelining Basics

  2. Sequential Processing

  3. Pipelined Processing

  4. Basic Steps of Execution 1. Instruction fetch step (IF) 2. Instruction decode/register fetch step (ID) 3. Execution/effective address step (EX) 4. Memory access (MEM) 5. Register write-back step (WB)

  5. Pipelined Instruction Execution • Sequential Execution • Pipelined Execution ADD $3, $1, $2 SUB $4, $5, $6 AND $7, $8, $9

  6. Basic Pipeline

  7. Major Hurdles of Pipelining • Structural Hazard • Data Hazard • Control Hazard

  8. Structural Hazard IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

  9. Solutions to Structural Hazard • Resource Duplication • example • Separate I and D caches for memory access conflict • Time-multiplexed or multi-port register file for register file access conflict

  10. Data Hazard (RAW hazard) ADD $1, $2, $3 SUB $4, $1, $5 IF ID EX MEM WB R W IF ID EX MEM WB R W Time

  11. Solutions to Data Hazard • Freezing the pipeline • (Internal) Forwarding • Compiler scheduling

  12. stall stall IF ID EX IF IF ID ID EX EX MEM MEM WB WB R R R W W stall stall IF ID EX R Freezing The Pipeline • ALU result to next instruction • Load result to next instruction ADD $1, $2, $3 SUB $4, $1, $5 LW $1, 32($6) SUB $4, $1, $5

  13. IF IF IF ID ID ID EX EX EX MEM MEM MEM WB WB WB R R R W W W stall IF ID EX MEM R (Internal) Forwarding • ALU result to next instruction (Stall X) • Load result to next instruction (Stall 1) ADD $1, $2, $3 SUB $4, $1, $5 LW $1, 32($6) SUB $4, $1, $5

  14. Control Hazard • Caused by PC-changing instructions (Branch, Jump, Call/Return) For 5-stage pipeline, 3 cycle penalty 15% branch frequency. CPI = 1.45

  15. Solutions to Control Hazard • Optimized branch processing • Branch prediction • Delayed branch

  16. Optimized Branch Processing 1. Find out branch taken or not early → simplified branch condition 2. Compute branch target address early → extra hardware

  17. Branch Prediction • Predict-not-taken

  18. Delayed Branch • Semantics of delayed branch

  19. Delayed Branch

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