Multiplier s Architecture

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2. Contents. Introduction Overview of MultiplicationUnsigned MultiplierSigned MultiplierSign Extension EliminationTypes of Multiplier ArchitecturesBraun MultiplierBaugh-Wooley MultiplierBooth MultiplierModified Booth MultiplierWallace Tree MultiplierDadda MultiplierCSD (Canonical Signed

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Multiplier s Architecture

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1. Multiplier’s Architecture

2. 2 Contents Introduction Overview of Multiplication Unsigned Multiplier Signed Multiplier Sign Extension Elimination Types of Multiplier Architectures Braun Multiplier Baugh-Wooley Multiplier Booth Multiplier Modified Booth Multiplier Wallace Tree Multiplier Dadda Multiplier CSD (Canonical Signed Digit) Multiplier

3. 3 Introduction Multiplication is an important fundamental function arithmetic operation Multiplication-based operations s.a. MAC & inner product DSP applications s.a. convolution, FFT, filtering, and so on Contribute significantly to the time delay and take up a great deal of silicon area in the system High speed multiplier is very desirable Multiplication time is still the dominant factor in determining the instruction cycle time When Word length is W The proportion of a complication of Adder to W The proportion of a complication of Multiplier to W2 Design emphasis has shift from optimizing conventional delay time and area size to minimizing power dissipation The subsequent sections present an overview of the multiplication operation and of different types of parallel multiplier

4. 4 Overview of Multiplication (1) Multiplication can be considered as a series of repeated additions Multiplicand : the number to be added Multiplier : the number of times it is added Product : the result obtained When M-bits (Multiplicand), N-bits (Multiplier) ? The number of NxM Partial Product needed Basic operation Generating and Accumulating or Adding the partial products The two main categories of binary arithmetic multiplication Unsigned numbers Signed numbers

5. 5 Overview of Multiplication (2) Unsigned multiplication (1) Real-time computer applications require fast multiplication By utilizing AND gates and Full adders Multiplication process Multiply each digit of the multiplier by multiplicand Generating partial products and then sum up the respective partial products

6. 6 Overview of Multiplication (3) Unsigned multiplication (2) Process of multiplying two unsigned BCDs using the paper-and-pencil method The partial storing of each partial product and the subsequent addition process involved make this method terribly inefficient

7. 7 Overview of Multiplication (4) Shift/add multiplication algorithms Initializing the cumulative partial product to “0” Adding to partial product the properly shifted terms of the multiplicand Two versions of algorithm Multiplication with right shift adds the partial product terms from top to bottom p(j+1) = (P(j) + Yj X 2n) 2-1 with p(0) = 0, p(n) = p Multiplication with right shift adds the partial product terms from bottom to top p(j+1) = 2P(j) + Yn-j-1 X with p(0) = 0, p(n) = p

8. 8 Unsigned Multiplier (1) 4x4 Multiplier Table

9. 9 Unsigned Multiplier (2) Addition Method 1 partial product using Ripple Carry Adder Generating Carry propagation at every time : Inconsistency

10. 10 Unsigned Multiplier (3) Addition Method 2 : partial product using Carry Save Adder

11. 11 Unsigned Multiplier (4) Implementation of Unsigned multiplier Using Carry Save Adder Array multiplier : ordering 1bit multiplier to two-dimension structures

12. 12 Unsigned Multiplier (5) 4x4 carry save multiplier including partial product generating circuit

13. 13 Signed Multiplier (1) Multiplication of signed number Procedure works well for unsigned integers or unsigned fixed-point numbers Negative number is first converted to its 2’s complement representation P ' = X (– Y ) = X ( 2n – Y ) = 2n X – XY P = – XY = 22n – XY P – P ' = 22n – 2n X = 2n ( 2n – X ) Both the multiplicand and multiplier are negative P ' = ( 2n – X ) ( 2n – Y ) = 22n – 2n X – 2n Y + XY P = XY P – P ' = – 22n + 2n X + 2n Y To get the correct result, correction factors for both multiplier and multiplicand should be added

14. 14 Signed Multiplier (2) When one of the multiplicand and multiplier is negative number ? Sign Extension

15. 15 Signed Multiplier (3) Because …

16. 16 Signed Multiplier (4) Sign Extension then

17. 17 Signed Multiplier (5) Negative Multiplier with sign extension

18. 18 Signed Multiplier (6) When both the multiplicand and multiplier are negative ? Converting Negative Multiplier to its 2’s complement representation

19. 19 Signed Multiplier (7) When the sign bit of Multiplier is ‘1’, the multiplier is a negative number Added after 2’ complement of partial product

20. 20 Sign Extension Elimination (1) Need overhead decrease by sign Extension

21. 21 Sign Extension Elimination (2) Ex :

22. 22 Sign Extension Elimination (3) Implementation of compensation vector decrease hardware complexity

23. 23 Types of Multiplier Architectures

24. 24 Braun Multiplier (1)

25. 25 Braun Multiplier (2)

26. 26 Braun Multiplier (3)

27. 27 Braun Multiplier (4)

28. 28 Braun Multiplier (5)

29. 29 Baugh-Wooley Multiplier (1)

30. 30 Baugh-Wooley Multiplier (2)

31. 31 Baugh-Wooley Multiplier (3)

32. 32 Baugh-Wooley Multiplier (4)

33. 33 Baugh-Wooley Multiplier (5)

34. 34 Baugh-Wooley Multiplier (6)

35. 35 Baugh-Wooley Multiplier (7)

36. 36 Baugh-Wooley Multiplier (8)

37. 37 Booth Multiplier (1) Braun multiplier & Baugh-Wooley multiplier achieve comparatively good performance but require large areas of silicon To increase the speed of Multiplier The decrease of the number of partial product Speed-up of the partial product accumulation Use of the Booth encoding algorithm Reduce the number of partial products by considering two bits of the multiplier at a time Achieve a speed advantage over other multiplier architectures Booth’s algorithm (Radix-2 algorithm) Multiplication accepts numbers in 2’s complement form, based on radix-2 computation Increases the complexity The signs of the operands get stored in auxiliary circuits

38. 38 Booth Multiplier (2) Recoding method used by the Booth’s theorem Output yi for 0=i=n is obtained by the following discrimination rule

39. 39 Modified Booth Multiplier (3) The rules for a standard radix-2 booth recoding 1. Append a zero to the right of the LSB of the multiplier 2. Inspect groups of two adjacent bits of the multiplier, starting with the LSB and the appended zero. If the pair is 00 or 11, Shift the partial product 1 bit to the right If the pair is 01, Add the multiplicand to the partial product and shift the partial product 1 bit to the right. If the pair is 10, Subtract the multiplicand from the partial product and shift the new partial product to the right by 1 bit. 3. Proceed with overlapping pairs of bits such that the MSB of a pair becomes the LSB of the next pair. 4. When the last pair of bits is examined, The partial product is updated following the rules except that no shift is performed.

40. 40 Modified Booth Multiplier (1) The shortcoming of Booth’s algorithm it becomes inefficient when there are isolated 1’s ? process 3 bits at a time during recoding Modified Booth Multiplier The decrease of the number of partial product Converting a factor of Multiplier to odd factors

41. 41 Modified Booth Multiplier (2)

42. 42 Modified Booth Multiplier (3) A coefficient of Modified Booth Coding

43. 43 Modified Booth Multiplier (4)

44. 44 Modified Booth Multiplier (5) 8 x 8 Modified Booth Multiplier

45. 45 Modified Booth Multiplier (6) Partial product table

46. 46 Wallace Tree Multiplier (1) Speed-up of Multiplier by decreasing the number of stage Grouping Partial product at an interval of three line and then adding. Otherwise, pass next stage. Finally, when remaining two line, calculation using fast adder and ripple carry adder

47. 47 Wallace Tree Multiplier (2) 4 x 4 Wallace Tree Multiplier Architecture

48. 48 Wallace Tree Multiplier (3) 8 x 8 Wallace Tree Multiplier Table

49. 49 Wallace Tree Multiplier (4) Multiplier using 4:2 Compressor Grouping partial product at an interval of 4-bits and then adding Speed-up of Accumulation, simple and regular connection Minimizing carry propagation by connecting that both Cout and Cin are an independent

50. 50 Wallace Tree Multiplier (5) Grouping of partial product for 4:2 Compressor

51. 51 Dadda Multiplier (1) The general form of Wallace Tree Multiplier When a line of partial product has next stage, possibly to reduces maximum 2/3 Executing minimum operation ( Current stage : p ? next stage : 2p/3 ) Compared with Wallace Tree Multiplier Reducing the number of adder Irregularity Increasing the size of carry propagation adder at final stage

52. 52 Dadda Multiplier (2) 8 x 8 Dadda Multiplier Table

53. 53 CSD (Canonical Signal Digit) Multiplier(1) Converting 2’complement of W-bits to CSD of W-bits Each bit have {1,0,-1}and have not successive non-zero bit Number of non-zero bits are less than 2’complement as 33% In the case of fixed coefficient Multiplier Using CSD Implementing economical Multiplier Ex : A = 0. 0 1 1 1 1 1 (1) Implementation using 2’ complement (2) Implementation using CSD 0. 0 1 1 1 1 1 = 0. 1 0 0 0 0 0 – 0. 0 0 0 0 0 1

54. 54 CSD (Canonical Signal Digit) Multiplier(2) Converted to CSD of 2’ complement Eliminating successive non-zero bit repeatedly Ex : 2’ complement A = 1. 0 1 1 1 0 0 1 1 = 1. 0 1 1 1 0 1 0 1 = 1. 1 0 0 1 0 1 0 1 = 1. 1 0 0 1 0 1 0 1 = 0. 1 0 0 1 0 1 0 1

55. 55 CSD (Canonical Signal Digit) Multiplier(3) Implementation of digital filter using CSD

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