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# Chapter 3c: Multiplication and Division PowerPoint PPT Presentation

Chapter 3c: Multiplication and Division. Multiplication. 4 2 1. Multiplying two numbers A and B. x 1 2 3. 1 2 6 3. n partial products, where B is n digits long. 8 4 2. + 4 2 1. 5 1 7 8 3. n additions. In Binary. 6 x 5. 1 1 0. Each partial product is either:

Chapter 3c: Multiplication and Division

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#### Presentation Transcript

Chapter 3c: Multiplication

and Division

### Multiplication

4 2 1

Multiplying two numbers A and B

x 1 2 3

1 2 6 3

n partial products, where B is n digits long

8 4 2

+ 4 2 1

5 1 7 8 3

In Binary...

6 x 5

1 1 0

Each partial product is either:

110 (A*1) or 000 (A*0)

x 1 0 1

1 1 0

0 0 0

+ 1 1 0

Equals 30

Note: Product may take as manyas two times the number of bits!

1 1 1 1 0

### Multiplication Steps

Step1: LSB of multiplier is 1 --> Add a copy of multiplicand

1 1 0 0

1 1 0

1 1 0 0 0

Step2: Shift multiplier right to reveal new LSBShift multiplicand left to multiply by 2

x

1 0

1 0 1

1

1 1 0

Step 3: LSB of multiplier is 0 --> Add zero

0 0 0 0

1 1 0 0 0

+

Step 4: Shift multiplier right, multiplicand left

0 0 1 1 0

1 1 1 1 0

Step5: LSB of multiplier is 1 --> Add a copy of multiplicand

Done!

Thus, we need hardware to:

1. Hold multiplier (32 bits) and shift it right

2. Hold multiplicand (32 bits) and shift it left (requires 64 bits)

3. Hold product (result) (64 bits)

4. Add the multiplicand to the current result

initialize registers;

Multiplicand

ShLeft

for (i=0; i<32; i++) {

64 bit

if LSB(multiplier)==1{

ShRight

Multiplier

product += multiplicand;

32 bit

}

64-bit

left shift multiplicand 1;

right shift multiplier 1;

Product

Write

64 bit

}

### Multiplication

We need hardware to:

1. Hold multiplier (32 bits) and shift it right

2. Hold multiplicand (32 bits) and shift it left (requires 64 bits)

3. Hold product (result) (64 bits)

4. Add the multiplicand to the current result

5. Control the whole process

Algorithm:

Control

xxxx1101

ShLeft

8 bit

ShRight

0101

4 bit

8-bit

Control

000000000

Write

8 bit

### Multiplication example: 1101 x 0101

MultiplicandMultiplierProduct

xxxx1101010100000000

Initial Values

• Shift M’cand left, M’plier right

+

xxx11010001000001101

• 0-->Do nothing

• Shift M’cand left, M’plier right

xx110100000100001101

+

x1101000000001000001

• Shift M’cand left, M’plier right

11010000000001000001

• 0-->Do nothing

• Shift M’cand left, M’plier right

1101 x 0101 = 0100000113 x 5 = 65

Note: Using 4/8 bit values forexample.

Assume unsigned integers.

ShRight

Multiplicand

Multiplier

32 bit

32 bit

Control

32-bit

Write

64 bit

ShRight

LH Product

RH Product

Algorithm:

initialize registers;

Multiplicand

ShLeft

for (i=0; i<32; i++) {

64 bit

if LSB(multiplier)==1{

ShRight

Multiplier

LH product += multiplicand;

32 bit

}

64-bit

right shift product 1;

Control

right shift multiplier 1;

Product

Write

64 bit

}

### Improved Multiplier

Even though we’re only adding 32 bits at a time, we need a 64-bit adder

Results from shifting multiplicand left over and over again

Instead, hold the multiplicand still and shift the product register right!

Now we’re only adding 32 bits each time

Extra bit for carryout

ShRight

Multiplicand

Multiplier

32 bit

32 bit

Control

32-bit

Write

0011+ 1101

10000

64 bit

ShRight

LH Product

RH Product

### Improved Multiplier: 1101 x 0101

MultiplicandMultiplierProduct

110101010000 xxxx

Initial Values

• 1-->Add Multiplicand to LH Product

• Shift Productright, M’plier right

+

110101011101 xxxx

1101x0100110 1xxx

• 0-->Do nothing

• Shift Product right, M’plier right

1101xx010011 01xx

+

• Shift Product right, M’plier right

1101xx0110000 01xx

1101xxx01000 001x

• 0-->Do nothing

• Shift Product right, M’plier right

1101xxxx0100 0001

1101 x 0101 = 0100000113 x 5 = 65

ShRight

Multiplicand

Multiplier

Multiplicand

32 bit

32 bit

32 bit

Control

32-bit

Control

32-bit

Algorithm:

Write

Write

64 bit

ShRight

initialize registers (multiplier in RH product);

LH Product

RH Product

ShRight

LH Product

Multiplier

64 bit

for (i=0; i<32; i++) {

if LSB(multiplier)==1{

LH product += multiplicand;

right shift product-multiplier 1;

}

}

### Improved Improved Multiplier

Note that we’re shifting bits out of the multiplier and into the product

Why not put these together into the same register

As space opens up in the multiplier, overwrite it with the product bits

0011+ 1101

10000

Multiplicand

32 bit

Control

32-bit

Write

ShRight

LH Product

Multiplier

64 bit

### Improved Multiplier: 1101 x 0101

MultiplicandProduct-Multiplier

110100000101

Initial Values

• 1-->Add Multiplicand to LH Product

• Shift Product-M’plier right

+

11011101 0101

11010110 1010

• 0-->Do nothing

• Shift Product-M’plier right

11010011 0101

+

• Shift Product-M’plier right

1101100000101

110110000010

• 0-->Do nothing

• Shift Product-M’plier right

11010100 0001

1101 x 0101 = 0100000113 x 5 = 65

Rs

32 bit

Control

32-bit

Write

ShRight

Hi

Lo

64 bit

### MIPS Multiplying

MIPS hardware does32-bit multiplies32-bit x 32-bit --> 64 bit

mult Rs, Rt -->Upper 32-bits of result in HiLower 32-bits of result in Lo

The 64-bit product register is divided into two parts:

Hi: Holds upper 32 bits of product

Lo: Holds lower 32 bits

mul Rd, Rs, Rt -->

mult Rs, Rt

mflo Rd

mfhi \$t5 # move Hi to register \$t5

mflo \$t6 # move Lo to register \$t6

-45

-000

-30

-101

-30

-101

-15

-101

-000

### Dividing

quotient

Dividend = Divisor * Quotient + Remainder

divisor

3

2

2

1

15

48323

dividend

14

5

3

3

0

1

1

1

0

101

1001001

3

2

73

100

1

2

3

remainder

100

0

8

11

0

Idea: Repeatedly subtract divisor. Shift as appropriate.

1

1

3

11

-000

-101

-101

-101

-000

### Dividing

Looking at the alignment a little differently…

0

1

1

1

0

0

1

1

1

0

0101

01001001

101

1001001

Make the dividend 8 bits and the divisor 4 bits by filling in with 0’s

-01010000

01001001

100

1

-00101000

Each iteration, re-express the entire remainder as 8 bits

Note: At any step, the dividend = divisor * quotient + current remainder

00100001

100

0

-00010100

00001101

11

0

-00001010

00000011

Try subtracting the divisor from the current remainder each time – if it doesn’t fit, restore the remainder

1

1

-00000101

00000011

11

Divisor

ShRight

64 bit

if (remainder< 0)

{

ShLeft

Quotient

remainder+=divisor;left shift quotient 1, LSB=0

32 bit

64-bit

} else {

left shift quotient 1, LSB=1

Control

}

Remainder

Write

right shift divisor 1

64 bit

}

### Division

We need hardware to:

1. Hold divisor (32 bits) and shift it right (requires 64 bits)

2. Hold remainder (64 bits)

3. Hold quotient (result) (32 bits) and shift it left

4. Subtract the divisor from the current result

Algorithm:

5. Control the whole process

initialize registers (divisor in LHS);

for (i=0; i<33; i++) {

remainder -= divisor;

### Limitations of Division

Our setup: 64-bit dividend, 32-bit divisor, 32-bit quotient

Some choices of divisor result in a quotient larger than 32 bits

0x 32F2 4823 9AB0 132F 8321 8923 8382 0123 / 1 = 0x 32F2 4823 9AB0 132F 8321 8923 8382 0123

If the division result requires > 32 bits, it cannot be represented(equivalent to overflow)

5

3

2

1

4

Divisor

ShRight

64 bit

ShLeft

Quotient

64-bit

32 bit

Remainder

Write

Control

64 bit

### Division Example: 1001001/0101

QuotientDivisorRemainder

xxxx0101000001001001

Initial Values (Divisor in LHS)

• 1a.Rem. <-- Rem-Divisor

-

• 1b.Rem.<0, Add Div., LSh Q, Q0=0; RSh Div.

xxxx0101000011111001

• 2a.Rem. <-- Rem-Divisor

xxx00010100001001001

• 2b.Rem>=0, LSh Q, Q0=1; RSh Div.

-

xxx00010100000100001

• 3a.Rem. <-- Rem-Divisor

• 3b.Rem>=0, LSh Q, Q0=1; RSh Div.

xx010001010000100001

-

• 4a.Rem. <-- Rem-Divisor

xx010001010000001101

• 4b.Rem>=0, LSh Q, Q0=1; RSh Div.

x0110000101000001101

• 5a.Rem. <-- Rem-Divisor

-

• 5b.Rem<0, Add Div., LSh Q, Q0=0; RSh Div.

x0110000101000000011

01110000010100000011

-

01110000010111111110

11100000001000000011

1001001/0101 = 1110 rem 001173/5 = 14 rem 3

N+1 Steps, but if 1st step produces a ‘1’ the result requires N+1 bits and cannot be represented

Algorithm:

initialize registers

for (i=0; i<32; i++) {

left shift remainder 1;

Divisor

Divisor

ShRight

32 bit

LH remainder -= divisor;

64 bit

ShLeft

if (remainder< 0)

Quotient

ShLeft

{

Quotient

LH remainder+=divisor;left shift quotient 1, LSB=0;

32 bit

32-bit

32 bit

64-bit

} else {

Write

Control

left shift quotient 1, LSB=1;

ShLeft

LH Rem.

RH Rem.

Control

}

Remainder

Write

64+1 bit

}

64 bit

Extra bit for shift out of MSB

### Improved Divider

As with multiplication, we’re using a 64-bit divisor and a 64-bit ALUwhen there are only 32 useful bits.

The 64-bit divisor is needed just to provide the correct alignment.

Instead of shifting the divisor right, we shift the remainder left.

However, we’ll occasionally shift a 1 out of the MSB (temporarily) – we’ll needan extra bit for that.

Also, since we know the first subtraction is useless,don’t do it (still shift the remainder left, though).(Changes from 33 iterations to 32!)

1

3

4

2

Divisor

32 bit

ShLeft

Quotient

32 bit

32-bit

Write

Control

ShLeft

LH Rem.

RH Rem.

64+1 bit

### Improved Divider: 1001001/0101

Initial Values

QuotientDivisorRemainder

xxxx010101001001

• 0. LSh Rem

• 1a.Rem. <-- Rem-Divisor

xxxx01011001001x

-

• 1b.Rem>=0, LSh Q, Q0=1; LSh Rem.

xxxx01010100001x

• 2a.Rem. <-- Rem-Divisor

xxx10101100001xx

• 2b.Rem>=0, LSh Q, Q0=1; LSh Rem.

-

xxx10101001101xx

• 3a.Rem. <-- Rem-Divisor

xx11010101101xxx

• 3b.Rem>=0, LSh Q, Q0=1; LSh Rem.

-

• 4a.Rem. <-- Rem-Divisor

xx11010100011xxx

• 4b.Rem<0, Add Div., LSh Q, Q0=0

x11101010011xxxx

-

x11101011110xxxx

111001010011xxxx

1001001/0101 = 1110 rem 001173/5 = 14 rem 3

Algorithm:

initialize registers

left shift rem-quotient 1;

Divisor

for (i=0; i<32; i++) {

Divisor

32 bit

LH remainder -= divisor;

32 bit

if (remainder< 0)

ShLeft

{

Quotient

LH remainder+=divisor;left shift rem-quotient 1, LSB=0;

32 bit

32-bit

32-bit

} else {

Write

Control

left shift rem-quotient 1, LSB=1;

Write

Control

ShLeft

LH Rem.

Rem-Quot.

}

ShLeft

LH Rem.

RH Rem.

64+1 bit

64 bit

}

### Improved Improved Divider

Note that the remainder is emptying at the same rate that the quotient is filling.

Combine the two!

A problem: We’re shifting the remainder left 33 times, but it should be 32. (Quotient doesn’t exist on first iteration, so it’s shifted only 32 times)

Undo the extra shift by shifting the remainder (LH remainder-quotient) right by1 at the end

right shift LH remainder-quotient 1

4

3

2

1

Divisor

32 bit

32-bit

Write

Control

ShLeft

LH Rem.

Rem-Quot.

64+1 bit

### Improved Improved Divider: 01110100/1001

Initial Values

DivisorRemainder-Quotient

100101110100

• 0. LSh Rem-Quo.

• 1a.Rem <-- Rem-Divisor

100111101000

-

• 1b.Rem>=0, LSh Rem-Quo, Q0=1

100101011000

• 2a.Rem. <-- Rem-Divisor

100110110001

• 2b.Rem>=0, LSh Rem-Quo,Q0=1

-

100100100001

• 3a.Rem. <-- Rem-Divisor

100101000011

• 3b.Rem>=0, LSh Rem-Quo, Q0=1

-

• 4a.Rem. <-- Rem-Divisor

100111010011

• 4b.Rem<0, Add Div., LSh Rem-Quo, Q0=0

100110000110

-

100111110110

1001100001100

• Final: RSh Rem 1

100110001100

01110100/1001 = 1100 rem 1000116/9 = 12 rem 8

Divisor

32 bit

32-bit

Write

Control

ShLeft

Hi

Lo

64 bit

### MIPS Dividing

MIPS hardware does64-bit / 32-bit division

Result has two parts:

Quotient in Lo

Remainder in Hi

div \$t1,\$t2Lo = \$t1/\$t2 (integer)Hi = \$t1 % \$t2

pseudoinstructions:

div \$t0, \$t1, \$t2\$t0 = \$t1/\$t2 (integer)rem \$t3, \$t1, \$t2\$t3 = \$t1 % \$t2