Wp8 5 2 electronics options
This presentation is the property of its rightful owner.
Sponsored Links
1 / 13

WP8.5.2 Electronics Options PowerPoint PPT Presentation


  • 72 Views
  • Uploaded on
  • Presentation posted in: General

WP8.5.2 Electronics Options. T2K ND280 TRIP-t DRS4(5) EASIROC/MAROC. DRS4. AIDA WP8.5.2 light yield estimates. EASIROC Description. Number of channels: 32 Analogue core : Internal input 8-bit DAC (0-4.5V) for individual SiPM gain adjustment

Download Presentation

WP8.5.2 Electronics Options

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Wp8 5 2 electronics options

WP8.5.2 Electronics Options

  • T2K ND280 TRIP-t

  • DRS4(5)

  • EASIROC/MAROC

DRS4


Aida wp8 5 2 light yield estimates

AIDA WP8.5.2 light yield estimates


Easiroc description

EASIROC Description

  • Number of channels: 32

  • Analogue core :

    • Internal input 8-bit DAC (0-4.5V) for individual SiPM gain adjustment

    • Individually addressable calibration injection capacitance

    • Energy measurement : 14-bit dynamic range

      • 2 tuneable gains followed by 2 adjustable shapers

      • Analogue memory (Track & Hold cell) for low gain and high gain

      • Common 10-bit DAC for threshold adjustment

      • Variable shaping time: from 25 ns to 175 ns

      • from 160 fC 320 pC (ie. 1 pe 2000 pe @ SiPM gain = 106)

      • pe/noise ratio : ~10 @ SiPM gain 106

    • Trigger output

      • pe/noise ratio on trigger channel : ~ 25

      • Fast shaper : ~15ns

      • Trigger on 50 fC (ie. 1/3 pe @ SiPM gain = 106)


Easiroc schematic

EASIROC Schematic


Easiroc evaluation board

EASIROC Evaluation Board

  • Enables tests of most of the functionality of the EASIROC.

  • Full access to slow control 456 bits.

  • Pins on I/O allow for easy monitoring.

  • External ADCs for analogue signal tests.

Courtesy IN2P3 Omega-LAL – 11/07/12


Test setup in bldg 595

Test setup in bldg. 595

PC

LabVIEW 10.0

DG 535 Pulse Generator

Scope

GPIB

OR32

EASIROC Test Board

USB

Power Supply


Trigger readout latched vs discr

Trigger readout: Latched vsDiscr.

Latch

Val Evt signal effect

Trigger output using latch

Direct

Trigger output in direct discriminator mode


Preamp f eedback tests

Preamp feedback tests


Shaper test i ii

Shaper test I/II

T&H is OR32 with programmable delay through FPGA


Shaper test ii ii

Shaper test II/II

50 ns time constant

80ns

12.5ns

50ns

125ns


Discriminator dac scan

Discriminator DAC Scan


Trigger or32 oscillations

Trigger/OR32 Oscillations

7: Quasi stable

5: Low unstable: extra OR32 pulses observed

4: High unstable: extra OR32 pulses observed

2: No signal – Low

3: No signal – High


Outlook

Outlook

PC

LabVIEW 10.0

SiPM

Scope

OR32

EASIROC Test Board

USB

Power Supply


  • Login