1 / 13

CSE 140 Lecture 16 System Designs II

CSE 140 Lecture 16 System Designs II. Professor CK Cheng CSE Dept. UC San Diego. System Designs. Methodology Hierarchy Flow and Process Technology-Oriented Construction. Design Process. Describe system in programs Data subsystem List data operations

rmelancon
Download Presentation

CSE 140 Lecture 16 System Designs II

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CSE 140 Lecture 16System Designs II Professor CK Cheng CSE Dept. UC San Diego

  2. System Designs • Methodology • Hierarchy • Flow and Process • Technology-Oriented Construction

  3. Design Process • Describe system in programs • Data subsystem • List data operations • Map operations to functional blocks • Add interconnect for data transport • Input control signals and output conditions • Control Subsystem • Derive the sequence according to the hardware program • Create the sequential machine • Input conditions and output control signals

  4. Example: Multiplication • Input X, Y • Output Z • Variable M, i • M<=0 • For i=n-1 to 0 • If Yn-1=1, M<=M+X • Shift Y left by one bit • If i != 0, shift M left by one bit • Z<=M Arithmetic Z=X x Y • M<=0 • For i=n-1 to 0 • If Yi=1, M<=M+X 2i • Z<=M

  5. Implementation: Example Multiply(X, Y, Z, start, done) { Input X[15:0], Y[15:0] type bit-vector, start type boolean; Local-Object A[15:0], B[15:0] ,M[31:0], i[4:0] type bit-vector; Output Z[31:0] type bit-vector, done type boolean; S0: If start’ goto S0; S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0; S2: If B15 = 0 goto S4 || i<=i+1; S3: M <= M+A; S4: if i>= 16, goto S6 S5: M<=Shift(M,L,1) || B<=Shift(B,L,1) || goto S2; S6: Z<= M || done<= 1|| goto S0; }

  6. Implementation: Example Multiply(X, Y, Z, start, done) { Input X[15:0], Y[15:0] type bit-vector, start type boolean; Local-Object A[15:0], B[15:0], M[31:0], i[4:0] type bit-vector; Output Z[31:0] type bit-vector, done type boolean; S0: If start’ goto S0; S1: A <= X || B <= Y || i<=0 || M<=0 || done <= 0; S2: If B15 = 0 goto S4 || i<=i+1; S3: M <= M+A; S4: if i>= 16, goto S6 S5: M<=Shift(M,L,1) || B<=Shift(B,L,1) || goto S2; S6: Z<= M || done<= 1|| goto S0; }

  7. Z=XY 16 32 X Data Subsystem Z 16 Y C0-7 B15, i4 Control Subsystem done start

  8. Data Path Subsystem operation A  Load (X) B  Load (Y) M Clear(M) i Clear(i) i  INC(i) M Add(M,A) M  SHL(M) B  SHL(B) Wires control C0 C2 C4 C6 C7 C5 C1 C3 A <= X B <=Y M<=0 i<=0 i<=i+ 1 M<=M+A M<=Shift(M,L,1) B<=Shift(B,L,1) Z<=M

  9. Data Path Subsystem Register A C1 Adder R D X A SHL 16 LD Z S D R B Shifter M CLR LD C0 C4 C5 Register B Counter i D R Y R D CLR Inc i[4] LD SHL B[15] C6 C7 Control Unit C2 C3 i[4] C0-7 B[15] done start

  10. Control Subsystem C1 A Add X SHL M 16 LD Z 16 CLR LD C0 C4 C5 i B i[4] Y CLR Inc LD SHL B[15] C6 C7 C2 C3

  11. Control Subsystem S6 S0 start’ start S1 S5 S2 i[4] i[4]’ B[15]’ B[15] S3 S4

  12. Summary • Hardware Allocation • Balance between cost and performance • Resource Sharing and Binding • Map operations to hardware • Interconnect Synthesis • Convey signal transports • Operation Scheduling • Sequence the process

  13. Exercises: • Implement the control subsystem with one-hot state machine design. • Try to reduce the latency of the whole system.

More Related