Computer science 101
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Computer Science 101. Computer Systems Organization MEMORY. Pappaw, our puter broke. What’s a man to do?. Perfectly clear, huh?. I think I’m getting a headache. Von Neumann Architecture. Basic Architecture of most computers Four Major Subunits Memory Input-output

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Computer Science 101

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Computer science 101

Computer Science 101

Computer Systems

Organization

MEMORY


Pappaw our puter broke

Pappaw, our puter broke.


What s a man to do

What’s a man to do?

Perfectly clear, huh?


I think i m getting a headache

I think I’m getting a headache.


Von neumann architecture

Von Neumann Architecture

  • Basic Architecture of most computers

  • Four Major Subunits

    • Memory

    • Input-output

    • Arithmetic-logic unit (ALU)

    • Control Unit

  • Stored Programs


Von neumann architecture1

Von Neumann Architecture

  • Execution Cycle

    • Fetch Instruction

    • Decode

    • Execute

HP Pavilion Media CenterProcessor speed: 2.8GHz

giga- G 1000^3  1024^3 = 2^30 = 1,073,741,824Hz- cycle per second2.8 billion cycles per second


Major components

Bus

Memory

Input

Output

Units

Control

Unit

ALU

CPU

Major Components

HP Pavilion Media CenterBus Speed: 800MHz Front Side Bus


Memory

Memory

  • Stores: Numbers, text, programs, addresses, graphics, sound, video, etc. that are currently in use.

  • Divided into fixed size cells (fixed number of bits).

  • This size is commonly 8 bits, and this 8-bit unit is called a byte.

  • The simple hypothetical lab machine uses 16 bit cells. The lab machine is a simulated version of a very simple, but illustrative computer.

HP Pavilion Media Center

Memory: 1024MB PC2-4200 DDR2 SDRAM memory (expandable to 2GB)


A bit is what the dentist uses to fix your byte

A bit is what the dentist uses to fix your byte?


Memory addresses

00100110

00111110

10100110

10101010

Memory Addresses

  • Each cell has an address, an unsigned integer.

  • All accesses to memory are via a specific address

AddressCell Content

0

1

2

3


Basic memory operations

Basic Memory Operations

  • Memory Fetch

    • Given a specific memory address.

    • Retrieve the content stored at that address.

  • Memory Store

    • Given a specific memory address and

    • a specific value,

    • store the given value in the cell with the specified address.


Memory fetch

00100110

00111110

10100110

10101010

Memory Fetch

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Content:


Memory fetch1

00100110

00111110

10100110

10101010

Memory Fetch

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Content:


Memory fetch2

00100110

00111110

10100110

10101010

Memory Fetch

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Content:


Memory fetch3

00100110

00111110

10100110

10101010

Memory Fetch

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Content:


Memory fetch4

00100110

00111110

10100110

10101010

Memory Fetch

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Content: 00111110


Memory store

AddressCell Content

2002

00100110

00111110

2003

10100110

10101010

2004

2005

Given Address: 2004

Given Value: 10101010

Memory Store


Memory store1

00100110

00111110

10100110

10101010

Memory Store

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Given Value: 10101010


Memory store2

00100110

00111110

10100110

10101010

Memory Store

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Given Value: 10101010


Memory store3

00100110

00111110

10100110

10101010

Memory Store

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Given Value: 10101010


Memory store4

00100110

10101010

10100110

10101010

Memory Store

AddressCell Content

2002

2003

2004

2005

Given Address: 2004

Given Value: 10101010


Memory facts and terminology

Memory Facts and Terminology

  • A cell is the minimum unit of access.

  • Access time is same for all cells - Random Access Memory or RAM (nanoseconds - billionths of second)

  • ROM - Read only Memory (fetch but not store)

  • Some data items require more than one cell. For example, an instruction might need four cells. Note: ints require 4 cells (bytes)


More on memory

More on Memory

  • All addresses are of some fixed number of bits, say N. Addresses would be0000…0  00000…1  1 Total of 2N cells …1111…1  2N – 1

  • Note: This is an application of unsigned numbers.


Terminology

Terminology

  • Storage capacity:

    • K  210 = 1024  Kilo as in Kb

    • M  220 = 1,048,576  Mega as in Mb

    • G  230 = 1,073,741,824  Giga as in Gb

  • Speed

    • 1  = 1 microsecond = 1 millionth of second

    • 1 ms = 1 millisecond = 1 thousandth of second

    • 1 ns = 1 nanosecond = 1 billionth of second

  • Cycle rate: Hertz is cycle per second


Memory registers

Memory Registers

  • A register is an extremely fast cell - more expensive than RAM cells - fewer of them - for special purposes.

  • MAR - Memory Address Register- size is same as size of an address - holds the address of the cell to access.

  • MDR - Memory Data Register- size is multiple of RAM cell size - holds content of cell fetched or value to be stored.


Mar and max memory size

HP Pavilion Media Center

Memory: 1024MB PC2-4200 DDR2 SDRAM memory (expandable to 2GB)

  • This HP has maximum memory of 2GB or 231; so MAR must be 31 bits.

MAR and Max Memory Size

  • MAR of size N bits gives 2N possible addresses; so up to 2N possible memory locations.


Memory fetch more detail

Memory Fetch- More Detail

  • Fetch (address) To obtain data at a given address:

    • Load address into MAR

    • Address is decoded and cell is selected

    • Contents of cell put into MDR


Fetch 10110

00100110

00111110

10100110

10101010

Fetch(10110)

AddressCell Content

10100

10101

10110

10111

MAR

10110

MDR

0011110


Memory store more detail

Memory Store- More Detail

  • Store (address,value) To store a given value at a given address:

    • Load address into MAR

    • Load value into MDR

    • Address is decoded and cell is selected

    • Value from MDR is put into the selected cell


Store 10110 11111111

00100110

00111110

10100110

10101010

Store(10110,11111111)

AddressCell Content

10100

10101

10110

11111111

10111

MAR

10110

MDR

11111111


Address decoding

00100110

00100110

00111110

10100110

10100110

10101010

MAR

---n---

00111110

2n lines

10101010

n to

2n

decoder

Address Decoding

  • Recall: Decoder has n inputs, 2n outputs, inputs select one output to be 1, others 0.


Address decoding cont

Address decoding (cont.)

  • Note: If we have 26 bit addresses, this allows for 226 = 64M cells.

  • In the diagram before, the decoder would have 26 input lines and 67,108,864 output lines.

  • That’s a lot of lines.


Two dimensional memory layout

Two-dimensional memory layout

  • Now picture the 64M memory laid out as a 2-dimensional grid. There would be 213 rows and 213 columns.

  • Suppose we use half of the address (13 bits) to choose a row and half to choose the column in order to locate the cell.

  • This would use two decoders - one for the row and one for the column.


Two dimensional memory layout1

Two-dimensional Memory Layout

  • Here we have 2* 213= 16384 lines as opposed to 67,108,864 as in 1-dimensional

MAR

13 13

n to

213

n to

213


Computer science 101

But what happened to those adders?


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