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Lecture#10. M. Mateen Yaqoob The University of Lahore Spring 2014. Instruction and Interrupt cycles. Interrupt Cycle. Instruction cycle. Interrupts Disabled. Interrupt cycle. Fetch, decode Next Instruction. Execute Instruction. START. Interrupts Enabled. HALT.

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lecture 10

Lecture#10

M. Mateen Yaqoob

The University of Lahore

Spring 2014

instruction and interrupt cycles
Instruction and Interrupt cycles

Interrupt Cycle

Instruction cycle

Interrupts Disabled

Interrupt

cycle

Fetch, decode

Next

Instruction

Execute

Instruction

START

Interrupts Enabled

HALT

i o and interrupt
I/O and Interrupt
  • Input-Output Configuration :
    • Input Register(INPR), Output Register(OUTR)
      • These two registers communicate with a communication interface serially and with the AC in parallel
      • Each quantity of information has eight bits of an alphanumeric code
i o and interrupt1
I/O and Interrupt
  • Input Flag(FGI), Output Flag(FGO)
    • FGI : set when INPR has information, clear when INPR is empty
    • FGO : set when operation is completed, clear when output device is active (for example a printer is in the process of printing)
i o instructions
I/O instructions
  • These instructions are executed with the clock transition associated with timing signal T3
  • For these instructions, D7=1 and I=1
  • The control function is distinguished by one of the bits in IR(6-11)
program interrupt
Program Interrupt
  • Program Interrupt
    • Two I/O Transfer Modes
      • 1) Programmed I/O
      • 2) Interrupt-initiated I/O (FGI FGO)
  • IEN: interrupt enable flip-flop
  • R: interrupt flip-flop
program interrupt1

256(return address)

0 BUN 1120

Main Program

Interrupt

Service Routine

1 BUN 0

0

PC = 1

255

256

1120

Interrupt

Here

Program Interrupt
  • Demonstration of the interrupt cycle :
    • The memory location at address 0 is the place for storing the return address
    • Interrupt Branch to memory location 1
    • Interrupt cycle IEN=0

Save Return

Address(PC) at 0

Jump to 1(PC=1)

quiz 2
Quiz#2
  • Perform following logic operations on R1=10101001 10000101 [5 marks]
    • CLEAR (L bits of R1)
    • SET (H bits of R1)
    • COMPLEMENT (L bits of R1)
  • For registers R0 to R15 in a 32 bit system: [5 marks]
    • What is the MUX size we use?
    • How many MUX we need?
    • How many select bit?
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