Stt ram feasibility study
Download
1 / 21

STT-RAM Feasibility Study - PowerPoint PPT Presentation


  • 84 Views
  • Uploaded on

STT-RAM Feasibility Study. Amr Amin UCLA Jan 2010. Outline. Introduction Memory Cell Cell Area Calculation Write Current Limitations Reading Techniques and Limitations Effect of Process Variations and Mismatch MTJ Feasible Region Area Minimization. Introduction.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' STT-RAM Feasibility Study' - richard-rivers


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Stt ram feasibility study

STT-RAM Feasibility Study

Amr Amin

UCLA

Jan 2010


Outline
Outline

  • Introduction

  • Memory Cell

  • Cell Area Calculation

  • Write Current Limitations

  • Reading Techniques and Limitations

  • Effect of Process Variations and Mismatch

  • MTJ Feasible Region

  • Area Minimization


Introduction
Introduction

  • The need for a universal memory

  • Brief history of magnetic device memories

  • Description of the MTJ device

  • Literature survey

  • Summary of the paper flow


Stt ram cell
STT-RAM Cell

  • Schematic diagram

  • Anti-parallelizing / Parallelizing currents

  • Read disturb problem

  • Cell layout

  • Basic cell area vs. access device width


Effective cell area
Effective Cell Area

  • This takes into account the overhead of:

    • Column MUX

    • Row decoder

    • Sense Amp

    • I/O circuits

  • Area optimization should also consider:

    • Optimum memory partitioning

    • Access transistor vs. column MUX areas


Write current limitations
Write Current Limitations

  • MOS drain current equation and fitting

  • Maximum allowed RP and RAP for certain write current(s)

  • Column MUX design (justification for using T-gates instead of P-transistors)

  • Effect of each of the four MUX devices on the maximum allowed resistances






Reading limitations
Reading Limitations

  • Current sensing

  • Voltage sensing


Constant read signal contours
Constant ‘Read’ Signal Contours

  • Voltage Sensing

  • Current Sensing


Process variations
Process Variations

  • MOS variations:

    • Min K and max VT

    • Reduce the maximum allowed RP and RAP

  • Mismatch:

    • Degrades sensitivity of the SA

    • Higher nominal read margin is required

  • MTJ variations:

    • MgO thickness and area variations

    • Distort the nominal feasible region of the MTJ



Mtj feasible region
MTJ Feasible Region

  • What is the MTJ feasible region in the RP­RAP plan given the following:

    • Desired write current

    • Desired basic cell area

    • Column MUX width

    • Certain technology

    • Certain variations (Yield)

    • Matching parameters (Yield)


Dec 2009 tape out
Dec-2009 Tape-out

  • IBM-90nm-CMOS

  • VWL = VDD = 1 V

  • IWR = 500 μA

  • Wa=2.56 μm

  • WP,MUX=16 μm

  • WN,MUX=8 μm

  • MOS K varies +/- 20%

  • MOS VT varies +/- 50mV

  • MTJ: RA = 2 Ω.μm2

  • MTJ: KRA = 34 Ω.μm2/nm

  • MTJ: TMR = 100%

  • MTJ: KTMR = 200 %/nm

  • MTJ: ΔtMgO = 0.2 Ao

  • Current Sensing: VR= 600 mV

  • Current Sensing: ΔIR= 20 μA


Sram area constraint
SRAM-Area Constraint

  • IBM-90nm-CMOS

  • VWL = VDD = 1 V

  • IWR = 500 μA

  • Wa=2.56 μm

  • WP,MUX=16 μm

  • WN,MUX=8 μm

  • MOS K varies +/- 20%

  • MOS VT varies +/- 50mV

  • MTJ: RA = 2 Ω.μm2

  • MTJ: KRA = 34 Ω.μm2/nm

  • MTJ: TMR = 100%

  • MTJ: KTMR = 200 %/nm

  • MTJ: ΔtMgO = 0.2 Ao

  • Current Sensing: VR= 600 mV

  • Current Sensing: ΔIR= 20 μA




Area minimization problem
Area Minimization Problem

  • Minimize: Effective cell area

  • Subject to:

    • MTJ resistances and write current value

    • MTJ variations

    • Parallelizing/Anti-parallelizing Write current equations

    • MOS variations and matching parameters

    • Speed must come into picture to constrain the optimum memory partitioning

  • May be able to formulate this into a standard optimization problem form that can be solved efficiently


Remaining issues
Remaining Issues

  • Analyzing Read/Write Speed and adding this as a constraint in the optimization problem

  • The same with power

  • More analysis is needed for the minimum required sensing signal (current or voltage)

    • CMOS mismatches and offset

    • Signal degradation due to MgO thickness variation

    • Possible signal degradation due to CMOS process variation (dependant on the SA implementation)

  • Regenerating all results for different technologies


ad