Sutirtha sanyal barcelona supercomputing center barcelona l.jpg
Sponsored Links
This presentation is the property of its rightful owner.
1 / 19

Sutirtha Sanyal (Barcelona Supercomputing Center, Barcelona) PowerPoint PPT Presentation

  • Updated On :
  • Presentation posted in: General

Sutirtha Sanyal (Barcelona Supercomputing Center, Barcelona). Accelerating Hardware Transactional Memory (HTM) with Dynamic Filtering of Privatized Data.

Related searches for Sutirtha Sanyal (Barcelona Supercomputing Center, Barcelona)

Download Presentation

Sutirtha Sanyal (Barcelona Supercomputing Center, Barcelona)

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript

Sutirtha sanyal barcelona supercomputing center barcelona l.jpg

Sutirtha Sanyal (Barcelona Supercomputing Center, Barcelona)

Accelerating Hardware Transactional Memory (HTM) with Dynamic Filtering of Privatized Data

Slide2 l.jpg

TM framework should be able to execute transactions as efficiently as possible even if defined in a coarse-grain fashion. Usually programmers will define transactions in this manner on a large piece of code.

An analysis shows that many variables accessed inside a transaction are not truly shared across multiple threads. Rather they are completely local to an individual thread.

Algorithm and implementations l.jpg


Algorithm and implementations4 l.jpg

  • We assume programmer has a-priori knowledge about some data structures which are thread-local and we require that programmer use a dual version of malloc, named local_malloc() for such structures.

  • To filter out stack accesses of the transaction ( and any function call made from within a transaction) we use stack pointer and frame pointer register.


Implementation of htm l.jpg


  • Implemented HTM is modeled after TCC (ISCA, 2004) in M5 (a full-system simulator from Umichgan, Ann-arbor).

  • It belongs to Lazy-Lazy class of TM, where conflict detection and global memory updation occur at commit time.

  • Aborts are cheap, Commits are expensive.

Implementation of htm cont l.jpg


  • Cache line is modified to track readset and writeset of a transaction.

  • Each individual thread is identified by their unique Process Control Block Base register value. (This is alpha specific).

  • Cache coherence protocol is modified to allow multiple updated copies of the same cache line.

  • At each store the address and value are inserted into a queue called commit queue.However if SL bit of that word is set, it does not get included.(explained later).

  • During commit, each store in the queue is replayed.

Implementation of htm cont7 l.jpg


  • Modifications incoherence protocol are following:

    A) Whenever a processor makes a write, it does not invalidate other copies. Hence a processor write does not generate bus write.

    B) Whenever a processor wants to read a value for the first time, it is forced to go to bus. But here other should not reply with their own modified value. Hence response to Bus Read request is deactivated. This means request ultmately gets staisfied by the non-spec level of memory.

Implementation of htm cont8 l.jpg


  • When a thread wants to commit, it locks the bus (first come, first serve mode) for the entire commit duration.

  • Other thread can execute their transaction or else they have to spin waiting for commit permission.

  • However as each store passes the common bus during commit, other thread snnops the address and invalidate themselves if there is a conflict.

  • A transaction is retried immediately if it is doomed.

Slide9 l.jpg


  • Cache line is augmented with new bits. R- denotes if the cache line is read in a transaction. W- denotes update to the cache line SL (Speculative Local)- One bit per word denotes if the word read or written is local to thread.

Slide10 l.jpg


  • TLB structure is not modified. However an earlier unused bit in the protection filed is used to hold the locality information of a page. (Bit number 21 in case of Alpha)

Slide11 l.jpg


  • To filter out stack access two new registers are added. They hold the stack bounds for current executing transaction.

Slide12 l.jpg

Source of speed-up

  • During commit a substantial amount of bus-bandwidth is saved which would otherwise be wasted on commiting local variables.

  • For local variables, commit is done by clearing SL bits in the corresponding cache line.

Results l.jpg


Filtered vs Unfiltered Read/Write set size (in bytes)

Speed up numbers l.jpg

SPEED-UP Numbers

Speed up numbers15 l.jpg

SPEED-UP Numbers

Speed up numbers16 l.jpg

SPEED-UP Numbers

Speed up numbers17 l.jpg

SPEED-UP Numbers

Average speed-up of 1.14x across STAMP benchmarks is observed for scalable TCC type of HTM.

Slide18 l.jpg

SEED-UP Numbers(Cont..)

Average speed-up of 1.24x across STAMP benchmarks is observed for conventional TCC type of HTM.

Slide19 l.jpg

Commit Expedition

Reduction in commit cycle time

  • Login