Spezielle anwendungen des vlsi entwurfs applied vlsi design
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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design. Jacob Maxa Results of Phase 3: ST65 Netlist 13.12.2012. Institute MD, University of Rostock. Challenge. Create a Verilog netlist for the ST65 technology Build upon NAND/NOR gatter 65 nm structure width

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Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design

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Spezielle anwendungen des vlsi entwurfs applied vlsi design

Spezielle Anwendungen des VLSI – EntwurfsApplied VLSI Design

Jacob Maxa

Results of Phase 3: ST65 Netlist

13.12.2012

Institute MD, University of Rostock


Challenge

Challenge

  • Create a Verilog netlist for the ST65 technology

    • Build upon NAND/NOR gatter

    • 65 nm structure width

  • Optimize design for the ST65 technology

    • Change adder types for 10, 13 and 14 bit width

      • Carrylookahead

      • Brent-Kung

      • Ripple Carry


Calculations postsynthesis

Calculations Postsynthesis


Calculations finals

Calculations Finals

Pdyn = 1 µW Pstat = 1 mW area = 3k VDD = 1,0 V


Calculations finals1

Calculations Finals

Pdyn = 1 µW Pstat = 1 mW area = 6k VDD = 1,3 V


Synopsys flags

Synopsys Flags

  • Flags

    • optimize_registers – move registers to decrease the negative slack

    • set_ungroupyour_filter – unfold the hierarchical structures

    • set_flatten true -design your_filter -effort high –minimize multiple_output-phase true

    • set_structure true -design your_filter -boolean true -boolean_effort high -timing true

    • set_max_area 3000 -ignore_tns

    • set_max_leakage_power 1 mW

    • set_max_dynamic_power 1 uW

    • set_cost_priority {max_delaymin_delaymax_capacitancemax_transitioncell_degradationmax_fanout}

  • Compiling

    • compile -map_effort high -power_effort high -ungroup_all -boundary_optimization–scan -auto_ungroupdelay

    • compile_ultra -incremental -retime


Results 1 2

Results (1/2)


Results 2 2

Results (2/2)


Spezielle anwendungen des vlsi entwurfs applied vlsi design

End

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