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Chapter 9: Input/Output

Chapter 9: Input/Output. The Architecture of Computer Hardware and Systems Software: An Information Technology Approach 3rd Edition, Irv Englander John Wiley and Sons  2003 Wilson Wong, Bentley College Linda Senne, Bentley College. Process. Input. Output. Basic Model.

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Chapter 9: Input/Output

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  1. Chapter 9: Input/Output The Architecture of Computer Hardware and Systems Software: An Information Technology Approach 3rd Edition, Irv Englander John Wiley and Sons 2003 Wilson Wong, Bentley College Linda Senne, Bentley College

  2. Process Input Output Basic Model • Processing speed or program execution • determined primarily by ability of I/O operations to stay ahead of processor. Chapter 9 Input / Output

  3. Input/Output • Regardless of CPU power, the usefulness of a computer system is dependent on I/O facilities. • Keyboard input, screen and print output, and disk storage/retrieve would not be possible. • No Internet • No networks Chapter 9 Input / Output

  4. Problems with I/O • I/O operations take a lot of computer time • Devices operate at different rates of speed • CPU much quicker than I/O operations • Many input and output devices all trying to do I/O – sometimes at the same time. Chapter 9 Input / Output

  5. I/O Considerations Speed Issues • CPU operates at speeds much faster than the fastest I/O device • Devices operate at different speeds • Bursts of data • Block data transfer required for some devices Coordination • Several devices perform I/O simultaneously • Unexpected input • Various input formats • Status information needed for each device Chapter 9 Input / Output

  6. Examples of I/O Devices Chapter 9 Input / Output

  7. Requirements • There must be a means for individually addressing different peripheral devices. • There must be a way in which peripheral devices can initiate communication with the CPU. • Required to allow the CPU to respond to unexpected inputs Chapter 9 Input / Output

  8. Requirements • Programmed I/O is suitable for slow devices. Faster devices must have sufficient means for transferring data between I/O and memory (preferably without involving the CPU) • A means for handling devices with extremely different control requirements. Chapter 9 Input / Output

  9. Last requirement • Suggests its not practical to connect I/O devices directly to the CPU without an interface module unique to the device • Format required by different devices will be different. • Incompatibility in speed between devices and CPU make synchronization difficult • Buffer • Bursts vs. Streams • Electromechanical control requirements must be met. • Example: motor head in a disk drive to disk track Chapter 9 Input / Output

  10. Simple I/O Configuration • Simplest – an I/O module is connected to a pair of I/O registers in the CPU via a bus. • Data registers in the I/O module serve the same role as LMC input and output baskets. • Baskets could be buffered (holding multiple inputs or outputs) Chapter 9 Input / Output

  11. Simple I/O Configuration Chapter 9 Input / Output

  12. I/O Modules Functions • Recognizes messages from device(s) addressed to it and accepts commands from the CPU • Provides a buffer where the data from memory can be held until it can be transferred to the disk • Provides the necessary registers and controls to perform a direct memory transfer • Physically controls the device • Copies data from its buffer to the device/from the CPU to its buffer • Notifies with interrupts Chapter 9 Input / Output

  13. Input/Output Modules • Programmed I/O • CPU controlled I/O • Interrupt Driven I/O • External input controls • Direct Memory Access Controllers • Method for transferring data between main memory and a device that bypasses the CPU Chapter 9 Input / Output

  14. Programmed I/O • A bus interface allows a direct transfer between the computer’s bus and a register within an I/O module that controls the particular device. Both input and output are handled similarly. The technique is known as programmed I/O. Chapter 9 Input / Output

  15. Programmed I/O • I/O data and address registers in CPU • One word transfers • Address information for each I/O device • LMC I/O capability for 100 devices • Full instruction fetch/execute cycle • Primary use: • keyboards • communication with I/O modules (see DMA) Chapter 9 Input / Output

  16. Programmed I/O Chapter 9 Input / Output

  17. Programmed I/O Example Chapter 9 Input / Output

  18. Programmed I/O Example Chapter 9 Input / Output

  19. Interrupts • Signal that causes the CPU to alter its normal flow on instruction execution • frees CPU from waiting for events • provides control for external input • Examples • unexpected input (Control – C) • abnormal situation (power failure) • illegal instructions • multitasking, multiprocessing Chapter 9 Input / Output

  20. The CPU - The Interrupt Cycle • Fetch / Execute cycle • Interrupt cycle START Fetch Next Instruction Execute Instruction HALT Interrupts Disabled Check/Process Interrupt Chapter 9 Input / Output

  21. Interrupt Terminology • Interrupt lines (hardware) • Interrupt request • Interrupt handlers • Program that services the interrupt • Also known as an interrupt routine • Process Control Block (PCB) • Located in a part of memory known as the stack area • All registers of a program are saved here before control is transferred to the interrupt handler Chapter 9 Input / Output

  22. Interrupt Terminology • Servicing the interrupt • suspends program in progress • saves pertinent information including last instruction executed and data values in registers in thePCB (process control block) • branches to interrupt handler Chapter 9 Input / Output

  23. Servicing an Interrupt Chapter 9 Input / Output

  24. Use of Interrupts • Notify that an external event has occurred • real-time or time-sensitive • Signal completion • printer ready or buffer full • Allocate CPU time • time sharing • Indicate abnormal event (CPU originates for notification and recovery) • illegal operation, hardware error • Software interrupts (make interrupt routines available for use by other programs) Chapter 9 Input / Output

  25. Multiple Interrupts • Identifying devices • Polling (checking for input in rotation) • Vectored interrupts (include address of interrupting device) • Interrupt priorities • Loss of data vs. task completion • Maskable (disabled) interrupts Chapter 9 Input / Output

  26. Polled Interrupts Chapter 9 Input / Output

  27. Vectored Interrupts Chapter 9 Input / Output

  28. Multiple Interrupts Example Chapter 9 Input / Output

  29. Direct Memory Access • Transferring large blocks of data • Direct transfer to and from memory • CPU not actively involved in transfer itself • Required conditions for DMA • The I/O interface and memory must be connected • The I/O module must be capable of reading and writing to memory • Conflicts between the CPU and the I/O module must be avoided Chapter 9 Input / Output

  30. DMA Instruction Set • Application program requests I/O service from operating system • privileged instructions (intended for use by OS program) • To initiate DMA, programmed I/O is used to send the following information: • location of data on I/O device (block on disk) • the starting location in memory • the size of the block • read/write • Interrupt to CPU upon completion Chapter 9 Input / Output

  31. DMA Initiation and Control Chapter 9 Input / Output

  32. Basic CPU-Memory-I/O Pathway* Chapter 9 Input / Output

  33. Bus Configuration Chapter 9 Input / Output

  34. Bus Characteristics • Data width in bits carried simultaneously • Throughput, i.e., data transfer rate in bits per second • Point-to-Point vs. Multipoint • Parallel vs. Serial • Use • Distance • Protocol Chapter 9 Input / Output

  35. Bus Hierarchy • Processor bus: on-chip • Cache bus (backside bus) • Memory bus (front-side bus) • connects the memory subsystem and processor • Local I/O bus • high-speed bus used to connect performance critical peripherals to memory and processor • Examples: PCI, VESA Local Bus • Standard I/O bus • connects slower peripherals (ISA) to Local I/O bus Chapter 9 Input / Output

  36. Wintel Bus Systems • ISA: Industry Standard Architecture • MCA: Micro Channel Architecture • EISA: Extended Industry Standard Architecture • Local Bus • PCI: Peripheral Component Interconnect (also Apple, Sun, Compaq Alpha Server) • VLB: VESA (Video Electronics Standards Association) Local Bus • AGP: Accelerated Graphics Port • Point-to-point channel from graphics controller to main memory • Co-exists with PCI Chapter 9 Input / Output

  37. External Interface Buses and Ports • Parallel port • Serial port • RS-232C and RS-422 buses • SCSI • Small Computer System Interface • USB, USB-2 • Universal Serial Bus • IEEE 1394 • Firewire • i.link Chapter 9 Input / Output

  38. SCSI Bus • ANSI standard but multiple variations • Really an I/O bus rather than simple interface • Supports multiple devices from a single SCSI port Chapter 9 Input / Output

  39. Root Hub Hub Hub USB • Multipoint bus • Hubs provide multiple connection points for I/O devices • Supports 127 devices Topology Example Hub Chapter 9 Input / Output

  40. USB and FireWire (IEEE 1394) • Both serial, multipoint bus specifications • Add/remove devices w/o powering down • Packet protocol for isochronous data transfer • Isochronous: delivery at regular time intervals • Guarantee specified throughput Chapter 9 Input / Output

  41. USB vs. FireWire • USB: slow to medium speed data transfer applications, i.e., storage devices • 12 Mbits/sec • USB-2: high-speed data transfer • 480Mbits/sec • FireWire: high-speed data transfer, i.e., full motion video with sound • 400 Mbits/sec to 3.2 Gbits/sec Chapter 9 Input / Output

  42. Typical FireWire Configuration • Network-like characteristics • Device controllers independent Chapter 9 Input / Output

  43. Channel Architecture • Used in IBM mainframe computers • Channel subsystem • Separate I/O processor that serves as a CPU for I/O operations • Channel control words • Programs that transfer data between memory and an I/O device using DMA • Subchannels • Connected to a control unit module through one or more channel paths • Similar role to a device controller Chapter 9 Input / Output

  44. I/O Channel Architecture Chapter 9 Input / Output

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