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ELEC 7770 Advanced VLSI Design Spring 2008 Clock Skew ProblemPowerPoint Presentation

ELEC 7770 Advanced VLSI Design Spring 2008 Clock Skew Problem

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ELEC 7770 Advanced VLSI Design Spring 2008 Clock Skew Problem

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ELEC 7770 Advanced VLSI Design Spring 2008 Clock Skew Problem

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ELEC 7770Advanced VLSI DesignSpring 2008Clock Skew Problem

Vishwani D. Agrawal

James J. Danaher Professor

ECE Department, Auburn University

Auburn, AL 36849

vagrawal@eng.auburn.edu

http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html

ELEC 7770: Advanced VLSI Design (Agrawal)

FF A

FF B

Comb.

Data_out

Data_in

CKA

CKB

CK

CKA

CKB

Single-cycle path delay

ELEC 7770: Advanced VLSI Design (Agrawal)

FF A

FF B

Comb.

Data_out

Data_in

CKA

CKB

CKA

CKB

Multi-cycle path delay

ELEC 7770: Advanced VLSI Design (Agrawal)

- Skew is the time delay of clock signal at a flip-flop with respect to some time reference.
- For a given layout each flip-flop has a skew, measured with respect to the a common reference.
- Skews of flip-flops separated by combinational paths affect the short-path and long-path constraints.

ELEC 7770: Advanced VLSI Design (Agrawal)

Combinational

Block

Delay:

FFi

CKi

FFj

CKj

δ(i,j) ≤ d(i,j) ≤ Δ(i,j)

xi

xj

xi and xj are arrival times of clock edges

ELEC 7770: Advanced VLSI Design (Agrawal)

Tck

CKi

xi

intended

Not intended

CKj

Thj

xj

δ(i,j)

xi + δ(i,j) ≥ xj + Thj

ELEC 7770: Advanced VLSI Design (Agrawal)

Tck

CKi

xi

Not intended

intended

CKj

xj

Tsj

Δ(i,j)

xi + Δ(i,j) ≤ xj + Tck – Tsj

ELEC 7770: Advanced VLSI Design (Agrawal)

Linear program:

Minimize Tck

Subject to:

For all flip-flop pairs (i,j),

xi + δ(i,j) ≥ xj + Thj

xi + Δ(i,j) ≤ xj + Tck – Tsj

ELEC 7770: Advanced VLSI Design (Agrawal)

xk

FFi

FFj

FFk

xi

Ri

Rj

Rk

CK

Ci

Cj

Ck

xj

Use Elmore delay formula to calculate xi, xj, xk.

ELEC 7770: Advanced VLSI Design (Agrawal)

- W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp. 55-63, Jan. 1948.

i

Rj

Ri

Rk

j

k

CK

Ci

Cj

Ck

Shared resistance:

Rii = Ri

Rij = Rji = Ri

Rik = Rki = Ri

Rjj = Ri + Rj

Rjk = Rkj = Ri + Rj

Rkk = Ri + Rj + Rk

ELEC 7770: Advanced VLSI Design (Agrawal)

Delay at node k, xk= 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )

= 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck]

ELEC 7770: Advanced VLSI Design (Agrawal)

Minimum delay

Maximum delay

, -

, -

A

1

, -

9, 10

H

3

j

, -

0, 0

3, 3

B

3

4, 4

i

E

1

G

2

6, 7

, -

, -

C

1

, -

6, 8

J

1

F

1

k

, -

, -

5, 5

D

2

, -

ELEC 7770: Advanced VLSI Design (Agrawal)

Linear program:Minimize Tck

Subject to:For all flip-flop pairs (i,j),

xi + δ(i,j) ≥ xj + Thj + q

xi + Δ(i,j) ≤ xj + Tck – Tsj – q

Where q is a constant

xi are variables, ximin ≤ xi

Tck is a variable

ELEC 7770: Advanced VLSI Design (Agrawal)

Linear program:Maximize q

Subject to:For all flip-flop pairs (i,j),

xi + δ(i,j) ≥ xj + Thj + q

xi + Δ(i,j) ≤ xj + Tck – Tsj – q

Where Tck is a constant

xi are variables, ximin ≤ xi

q is a variable

ELEC 7770: Advanced VLSI Design (Agrawal)

No solution because of

zero slack.

Increasing skew tolerance q

Increasing clock period Tck

ELEC 7770: Advanced VLSI Design (Agrawal)

- N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.
- J. P. Fishburn, “Clock Skew Optimization,” IEEE Trans. Computers, vol. 39, no. 7, pp. 945-951, July 1990.

ELEC 7770: Advanced VLSI Design (Agrawal)