Lecture 4 Combinational Logic Implementation Technologies

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Lecture 4 Combinational Logic Implementation Technologies

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Lecture 4 Combinational Logic Implementation Technologies

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Lecture 4Combinational Logic Implementation Technologies

Prith Banerjee

ECE C03

Advanced Digital Design

Spring 1998

ECE C03 Lecture 4

- Review of Combinational Logic Technologies
- Programmable Logic Devices (PLA, PAL)
- MOS Transistor Logic
- READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, 5.5 5.6, 5.7, 6.2

ECE C03 Lecture 4

- Until now, we learned about designing Boolean functions using discrete logic gates
- We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure
- Specific functions can be programmed
- Can use programmable logic arrays (PLA) or programmable array logic (PAL)

ECE C03 Lecture 4

Pre-fabricated building block of many AND/OR gates (or NOR, NAND)

"Personalized" by making or breaking connections among the gates

Programmable Array Block Diagram for Sum of Products Form

ECE C03 Lecture 4

Equations

F0 = A + B' C'

F1 = A C' + A B

F2 = B' C' + A B

F3 = B' C + A

Key to Success: Shared Product Terms

Example:

Input Side:

1 = asserted in term

0 = negated in term

- = does not participate

Personality Matrix

Output Side:

1 = term connected to output

0 = no connection to output

ECE C03 Lecture 4

All possible connections are available

before programming

ECE C03 Lecture 4

Unwanted connections are "blown"

Note: some array structures

work by making connections

rather than breaking them

ECE C03 Lecture 4

Short-hand notation

so we don't have to

draw all the wires!

Notation for implementing

F0 = A B + A' B'

F1 = C D' + C' D

ECE C03 Lecture 4

Multiple functions of A, B, C

ABC

A

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A xor B xor C

F6 = A xnor B xnor C

B

C

A

B

C

ABC

ABC

ABC

ABC

ABC

ABC

ABC

ECE C03 Lecture 4

F1

F2

F3

F4

F5

F6

PAL concept — implemented by Monolithic Memories

constrained topology of the OR Array

A given column of the OR array

has access to only a subset of

the possible product terms

PLA concept — generalized topologies in AND and OR planes

ECE C03 Lecture 4

A

A

AB

AB

00

01

11

10

00

01

11

10

CD

CD

00

0

0

X

1

00

0

1

X

0

01

0

1

X

1

01

0

1

X

0

D

D

0

1

X

X

0

0

X

X

11

11

C

C

10

10

0

1

X

X

0

0

X

X

B

B

K-map for

W

K-map for

X

A

A

AB

AB

00

01

11

10

00

01

11

10

CD

CD

00

0

1

X

0

00

0

0

X

1

01

0

1

X

0

01

1

0

X

0

D

D

1

1

X

X

0

1

X

X

11

11

C

C

10

10

1

1

X

X

1

0

X

X

B

B

K-map for

Y

K-map for

Z

Truth Table

K-maps

Minimized Functions:

W = A + B D + B C

X = B C'

Y = B + C

Z = A'B'C'D + B C D + A D' + B' C D'

ECE C03 Lecture 4

0

0

0

0

0

0

A B C D

ECE C03 Lecture 4

4 product terms per each OR gate

\

A

D

1

\

D

\

B

\

D

\

C

1: 7404 hex inverters

2,5: 7400 quad 2-input NAND

\

B

3: 7410

t

ri 3-input NAND

4: 7420 dual 4-input NAND

\A

A

1

\B

4

\C

B

D

2

3

W

D

B

C

3

B

2

D

C

4

4

Z

A

5

B

2

1

X

2

C

1

C

3

2

Y

B

1

4 SSI Packages vs. 1 PLA/PAL Package!

ECE C03 Lecture 4

A

A

AB

AB

00

01

11

10

00

01

11

10

CD

CD

00

1

0

0

0

00

0

1

1

1

01

0

1

0

0

01

1

0

1

1

D

D

11

0

0

1

0

11

1

1

0

1

C

C

10

0

0

0

1

10

1

1

1

0

B

B

K-map for

EQ

K-map for

NE

A

A

AB

AB

00

01

11

10

00

01

11

10

CD

CD

00

00

0

0

0

0

0

1

1

1

1

0

0

0

0

0

1

1

01

01

D

D

11

1

1

0

1

11

0

0

0

0

C

C

10

1

1

0

0

10

0

0

1

0

B

B

K-map for

L

T

K-map for

GT

ABCD

ABCD

ABCD

ABCD

AC

AC

BD

BD

ABD

BCD

ABC

BCD

EQ

NE

LT

GT

ECE C03 Lecture 4

So far we have seen:

AND-OR-Invert

PAL/PLA

Generalized Building Blocks

Beyond Simple Gates

Kinds of "Non-gate logic":

• switching circuits built from CMOS transmission gates

• multiplexer/selecter functions

• decoders

• tri-state and open collector gates

• read-only memories

ECE C03 Lecture 4

Voltage Controlled Switches

n-type Si

p-type Si

"n-Channel MOS"

Metal Gate, Oxide, Silicon Sandwich

Diffusion regions: negatively charged ions driven into Si surface

Si Bulk: positively charged ions

By "pulling" electrons to the surface, a conducting channel is formed

ECE C03 Lecture 4

Voltage Controlled Switches

Logic 1 on gate,

Source and Drain connected

Logic 0 on gate,

Source and Drain connected

ECE C03 Lecture 4

+5V

+5V

+5V

Logic Gates from Switches

A

B

A

B

A B

A

A

A + B

NOR Gate

NAND Gate

Inverter

Pull-up network constructed from pMOS transistors

Pull-down network constructed from nMOS transistors

ECE C03 Lecture 4

+5V

+5V

Inverter Operation

"1"

"0"

"0"

"1"

Input is 1

Pull-up does not conduct

Pull-down conducts

Output connected to GND

Input is 0

Pull-up conducts

Pull-down does not conduct

Output connected to VDD

ECE C03 Lecture 4

+5V

+5V

NAND Gate Operation

"1"

"0"

"1"

"1"

"0"

"1"

A = 0, B = 1

Pull-up network has path to VDD

Pull-down network path broken

Output node connected to VDD

A = 1, B = 1

Pull-up network does not conduct

Pull-down network conducts

Output node connected to GND

ECE C03 Lecture 4

+5V

+5V

NOR Gate Operation

"0"

"1"

"0"

"0"

"1"

"0"

A = 0, B = 0

Pull-up network conducts

Pull-down network broken

Output node at VDD

A = 1, B = 0

Pull-up network broken

Pull-down network conducts

Output node at GND

ECE C03 Lecture 4

nMOS transistors good at passing 0's but bad at passing 1's

pMOS transistors good at passing 1's but bad at passing 0's

perfect "transmission" gate places these in parallel:

Control

Control

Control

In

Out

In

Out

In

Out

Control

Control

Control

Transmission or

"Butterfly" Gate

Switches

Transistors

ECE C03 Lecture 4

S

I

0

S

Z

S

I

1

Selector:

Choose I0 if S = 0

Choose I1 if S = 1

S

S

Z

0

Demultiplexer:

I to Z0 if S = 0

I to Z1 if S = 1

S

S

I

Z

1

S

ECE C03 Lecture 4

A

Y

Demultiplexers

Multiplexers

B

Z

A

Y

Demultiplexers

Multiplexers

B

Z

So far, we've only seen point-to-point connections among gates

Mux/Demux used to implement multiple source/multiple destination

interconnect

ECE C03 Lecture 4

Problem with the Demux implementation:

multiple outputs, but only one connected to the input!

S

Z

0

S

"0"

I

S

S

Z

1

S

"0"

S

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"

ECE C03 Lecture 4

I

1

I

1

"0"

One

"0"

One

"1"

Zero

"0"

"1"

Zero

"0"

N Input Tally Circuit: count # of 1's in the inputs

Straight Through

Diagonal

Conventional Logic

for 1 Input Tally

Function

Switch Logic Implementation

of Tally Function

ECE C03 Lecture 4

"0"

"0"

One

"0"

"0"

One

"1"

Zero

"0"

"1"

Zero

"0"

Operation of the 1 Input Tally Circuit

Input is 0, straight through switches enabled

ECE C03 Lecture 4

"1"

"0"

One

"1"

"0"

One

"1"

Zero

"0"

"1"

Zero

"0"

Operation of 1 input Tally Circuit

Input = 1, diagonal switches enabled

ECE C03 Lecture 4

I

I

I

Zero

One

T

wo

1

1

2

I

0

0

1

0

0

2

0

1

0

1

0

1

0

0

1

0

1

1

0

0

1

T

wo

Extension to the 2-input case

Zero

One

Conventional logic implementation

ECE C03 Lecture 4

I

1

Switch Logic Implementation: 2-input Tally Circuit

I

I

2

2

"0"

Two

Two

One

"0"

"0"

One

Zero

"1"

Zero

"0"

"0"

I

1

One

"0"

One

Cascade the 1-input implementation!

Zero

"1"

Zero

"0"

"0"

ECE C03 Lecture 4

Operation of 2-input implementation

"0"

"0"

"1"

"0"

"0"

"0"

"0"

"0"

One

One

"0"

"1"

"0"

"0"

Zero

Zero

"1"

"0"

"1"

"1"

"0"

"0"

"0"

"0"

"1"

"1"

"0"

"1"

"0"

"0"

"0"

"1"

One

One

"0"

"1"

"0"

"0"

Zero

Zero

"1"

"0"

"1"

"0"

"0"

"0"

"0"

"0"

ECE C03 Lecture 4

- Review of Combinational Logic Implementation Technologies
- Programmable Logic Devices (PLA, PAL)
- MOS Transistor Logic
- NEXT LECTURE: Combinational Logic Implementation with Multiplexers, Decoders, ROMS and FPGAs
- READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7

ECE C03 Lecture 4