Demonstration of Chalcogenide Based Non Volatile Memory
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Demonstration of Chalcogenide Based Non Volatile Memory 10 September, 2003 J. Rodgers, J. Maimon, L. Burcin, K. Hunt. Work sponsored by the Space Vehicles Directorate of the Air Force Research Laboratory. Presentation Outline. C-RAM Overview CTCV Radiation Test Results

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Work sponsored by the space vehicles directorate of the air force research laboratory

Demonstration of Chalcogenide Based Non Volatile Memory10September, 2003J. Rodgers, J. Maimon, L. Burcin, K. Hunt

Work sponsored by the Space Vehicles Directorate

of the Air Force Research Laboratory


Presentation outline

Presentation Outline

  • C-RAM Overview

  • CTCV Radiation Test Results

  • Recent Base Contract Status

  • FPGA Applicability

  • C-RAM NVRAM Roadmap


Chalcogenide phase change memory technology

Chalcogenide Phase Change Memory Technology

  • Chalcogenides: alloys with at least one Group VI element

    • C-RAM uses a Ge-Sb-Te alloy

    • Can exist in either of two stable states

    • Rapid, reversible transition between states

    • Used in CD-RW and DVD-RW applications (same alloy, thickness and deposition techniques)

Polycrystalline State

High reflectance

Low resistance

Amorphous State

Low reflectance

High resistance


Chalcogenide phase change memory technology1

Chalcogenide Phase Change Memory Technology

  • Three modes of operation –

    • Set ( Write a “1” )

      • Apply current to raise

        memory element temperature

        to promote crystallization

    • Reset ( Write a “0” )

      • Apply current to melt

        memory element

      • Cool quickly to “freeze-in”

        amorphous state

    • Read

      • Low voltage is applied, current determined by resistance of memory element

        • Amorphous state = high resistance = low current

        • Crystalline state = low resistance = high current


Chalcogenide phase change memory technology c ram strengths

Chalcogenide Phase Change Memory TechnologyC-RAM Strengths

  • Endurance (>109 cycles demonstrated)

  • Compact cell (1T1R)

  • Large dynamic range

  • Mature thin film technology

  • Excellent retention (10 years 120°C)

  • Compatible with CMOS

  • No special packaging considerations

  • Low programming current ~1mA / bit

  • Low voltage operation: 3.3V

  • Fast read, fast write (10-40 ns)

  • Radiation hard - should reflect response of base technology


Chalcogenide phase change memory technology2

Inserted Chalcogenide process steps after transistor processing and before first metal level

Demonstrated no effect on radiation or other characteristics of transistors

Demonstrated one transistor, one chalcogenide resistor memory cell (1T1R)

W

Stud

Top Electrode

Chalcogenide

Metal 1

TopElectrode

W

Stud

W

Chalcogenide

Stud

Bottom

Electrode

Bottom Electrode

Transistor

Chalcogenide Phase Change Memory Technology

Integration With CMOS


Chalcogenide technology characterization vehicle ctcv

64Kb

64Kb

32Kb

32Kb

Sub-chip 1: Four Separate Memory Arrays

Chalcogenide Technology Characterization Vehicle (CTCV)

  • Four independently packaged sub-chips

  • Sub-chips have variations in:

    • Cell size and layout

    • Sense amplifier type

      • Single-ended

      • Differential

      • Analog output

  • Total of 11 stand alone memory arrays

    • Six 64Kb arrays ( 4Kb x 16 )

    • Four 32Kb arrays ( 4Kb x 8 )

    • One 2kb array ( 256b x 8 )

  • Directly accessible discrete circuit and sub array elements


Work sponsored by the space vehicles directorate of the air force research laboratory

Chalcogenide Technology Characterization Vehicle (CTCV)

  • First pass silicon successful:

    • Demonstrated over 99.9% fully functional bits on all array variations tested to date

      • some arrays 100% fully functional

      • test chip design does not include redundancy bits

    • Operation from -55oC to 125oC verified

    • Operation over 3.3V +/- 10% verified

    • Demonstrated <100 ns write cycle and read access time


Ctcv radiation test results total ionizing dose

CTCV Radiation Test ResultsTotal Ionizing Dose

  • Cobalt 60 source, 61.4 Rad(Si)/s, through 2M Rad

  • Tested 4 parts, 3 with arrays and 1 with standalone read/write circuits

  • Discrete cell (1T1R) response shows no shift in programmed resistance or write currents

  • Stand-alone Sense Amp shows no shift in operating point


Ctcv radiation test results total ionizing dose1

CTCV Radiation Test ResultsTotal Ionizing Dose

  • Stand-alone Write Current Generators show ~0.3mA shift (> 20%)

  • Transistor with VGS near VT used to regulate current (external bias)

  • Current sensitive to small shifts in VT (  [VGS - VT]2 )

  • Shift due to external bias control, not chalcogenide memory elements

  • Results will be used to design write current generator for prototype


Ctcv radiation test results total ionizing dose2

CTCV Radiation Test ResultsTotal Ionizing Dose

  • 32K bit & 64K bit arrays

    • No functional fails through 2MRad(Si)

      • Requires adjustment in external biases for write currents

    • IDDQ decreased 20% on 2 arrays, steady for 4 arrays

      Conclusion: Chalcogenide memory element not affected by TID

Module - Array


Ctcv radiation test results single event effects

CTCV Radiation Test ResultsSingle Event Effects

  • Heavy Ion Testing at UC Berkeley - Feb ‘03

    • Static SEU test shows no upsets to LETeff of 98 MeV/mg/cm2 (maximum achievable with 4.5 MeV/amu cocktail)

    • No SEL observed

    • Chalcogenide memory element not affected by heavy ions


Ctcv radiation test results single event effects1

CTCV Radiation Test ResultsSingle Event Effects

  • Heavy Ion Testing at Brookhaven National Labs - July ‘03

    • Dynamic SEU Testing

  • No SEL observed to LETeff of 123 MeV/mg/cm2 (125oC, 3.63V) (maximum LETeff tested)

  • NO SEGR or other permanent effects observed

  • Two sensitive peripheral circuits with small error cross-sections identified

    • Transient read of high resistance state

    • False write during read of low resistance state


Ctcv radiation test results single event effects2

CTCV Radiation Test ResultsSingle Event Effects

  • Dynamic SEU revealed a transient read error

    • Small error cross-section

    • Sense amp sensitive to read of high resistance state

    • Projected fail rate: 685 years between upsets

    • Error rate scales only with number of sense amps and sub-block size

    • Improved sense amp design will be implemented for prototype device


Ctcv radiation test results single event effects3

CTCV Radiation Test ResultsSingle Event Effects

  • Dynamic SEU also revealed a cell data upset during read

    • Small error cross-section and only observed above LETeff of 59 MeV/mg/cm2

    • Write driver activated during read cycle

    • Low resistance re-programmed to high resistance

    • No permanent damage to cell - able to re-write on next cycle

    • Projected fail rate: 9 million years between upsets

    • Easily eliminated with dual path control for write circuit


Recent base contract status

Recent Base Contract Status

  • Running short loops in 0.25u process to demonstrate transition and resolve remaining prototype design issues

    • Sense amp, Write circuitry, Mask levels, Contacts

  • Ongoing CTCV testing to complete characterization test plan

    • Write endurance, Stability, Pattern sensitivity

  • Shipped parts to government labs for additional testing (Crane, Sandia, Goddard, JPL, AFRL)

  • Translated test chip to new 0.25 micron process and incorporated into demonstration vehicle for foundry modernization to be fabricated 4Q03

  • Recent Proposal Activity - 4M proposal in negotiations; Submitted DUS&T proposal for Universal Memory


Benefits of c ram based nv fpga

Benefits of C-RAM Based NV FPGA

  • Single-chip solution

    • No external EEPROM storage required for reload

  • “Live at power up”

    • near instantaneous boot up

  • Secure configuration protection

  • Re-programmability & Reconfigurability

  • SEU immunity in a radiation environment

    • No need to TMR configuration registers

    • No need for scrubbing

    • No need to periodically reload configuration registers

  • Total Dose immunity from Manassas base technology

  • Latchup immune

  • Potential applications:

    • FPGA configuration bits

    • DSP filter configuration bits

    • ADC linearity correction

    • On-chip analog circuit gain trim


C ram based fpga

C-RAM Based FPGA

  • Challenges:

    • Low power; Draws no steady-state current

    • “Reasonably” small to maintain density

  • Solutions:

    • C-RAM memory cell for embedded memory

    • Chalcogenide based latch for configuration elements

  • Status:

    • C-RAM memory cell embeddable in 0.15 micron logic

    • Chalcogenide based latch designed, simulated, scaling ongoing


C ram roadmap

C-RAM Roadmap

2003

2004

2005

2006

2007

2008

C-RAM Technology Program

0.15 m

Manassas

>Endurance

>Speed

Multi-

State

Diode

Technology

0.25 m

Manassas

CRAM Memory Products

4Mb

Flight

16Mb

Stack

1-4Mb Prototype

16Mb Flight

64Mb

Stack

16Mb Prototype

Universal Memory

Other CRAM Products

250K-1M gate FPGA

256K

Flight

1M

Flight

Embedded C-RAM

Multi-state (TrimResistor, Relay)

Multi-state memory


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