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Impulsive Noise Mitigation in OFDM Systems

Prof . Brian L. Evans, Embedded Signal Processing Laboratory, The University of Texas at Austin Students: Jing Lin, Yousof Mortazavi , Marcel Nassar , Karl Nieman.

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Impulsive Noise Mitigation in OFDM Systems

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  1. Prof. Brian L. Evans, Embedded Signal Processing Laboratory, The University of Texas at Austin Students: Jing Lin, YousofMortazavi, Marcel Nassar, Karl Nieman Objective: Use National Instruments’ DSP Design Module and RF/Comms tools to implement FPGA-based impulsive noise mitigation testbed. NI Embedded Controller (NI PXIe-8133) OFDM IMPULSIVE NOISE IN WIRELESS RECEIVERS • Noise Measurement Throughput of Wi-Fi Channel 7 [J. Shi et al., 2006] • Computational Platform • Clocks, busses, processors • Co-located transceivers PXI Chassis Sources of impulsive noise • OFDM transmits data over multiple independent subcarriers (tones) NI Flex RIO (NI PXIe-7965R) Antennas NI PXIe Chassis (NI PXIe-1082) Time • Background Voltage Equalizer and detector Receiver y x + IFFT Filter FFT + + - Vectorof symbolamplitudes(complex) Impulsive noise estimation Gaussian (w) + ImpulsiveNoise (e) Conventional OFDM system Channel Impulsive Noise Mitigation in OFDM Systems Added in our system Non-Communication Sources Electromagnetic radiation • FFT spreads out impulsive noise across all subcarriers Wireless Communication Sources Uncoordinated Transmissions Baseband processor SBL OFDM Test System Powered by NI SPARSE BAYESIAN LEARNING (SBL) LabVIEW Front Panel • N FFT bins (tones), M null tones • Transmitted null tones have zero power, received null tones contain noise • Exploit sparse structure of noise in time domain • Maximum-likelihood estimate using iterative Expectation Maximization • Each iteration requires 5 computations involving • NxM <-> MxN matrix-matrix multiplies • MxN<-> Nx1matrix-vector multiplies • MxM matrix inverse • Nx1 vector norm • In our system • N = 128, M = 32 • number of iterations = 30 • System implemented in NI hardware using DSP Design Module • Some software processing necessary due to matrix inverse • Actively investigating inversion methods suited for FPGA |J| x N RT Host (software) NI LabVIEW RT Simulator SBL Software NI LabVIEWFPGA DSP Design Module ~10dB FPGA (hardware) ~6dB SBL Hardware DSP Design Diagram J is set of null tones (i.e. xj= 0)F is N x NDFT matrix Project supported by National Instruments

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