Loading in 5 sec....

ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle ControllerPowerPoint Presentation

ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller

Download Presentation

ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller

Loading in 2 Seconds...

- 102 Views
- Uploaded on
- Presentation posted in: General

ECE 361 Computer Architecture Lecture 11: Designing a Multiple Cycle Controller

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

ECE 361Computer ArchitectureLecture 11: Designing a Multiple Cycle Controller

- The root of the single cycle processor’s problems:
- The cycle time has to be long enough for the slowest instruction

- Solution:
- Break the instruction into smaller steps
- Execute each step (instead of the entire instruction) in one cycle
- Cycle time: time it takes to execute the longest step
- Keep all the steps to have similar length

- This is the essence of the multiple cycle processor

- The advantages of the multiple cycle processor:
- Cycle time is much shorter
- Different instructions take different number of cycles to complete
- Load takes five cycles
- Jump only takes three cycles

- Allows a functional unit to be used more than once per instruction

ALU

32

ALU

Control

32

- Every cycle begins right AFTER the clock tick:
- mem[PC] PC<31:0> + 4

Clk

One “Logic” Clock Cycle

You are here!

PCWr=?

PC

32

MemWr=?

IRWr=?

32

32

RAdr

Clk

4

32

Ideal

Memory

Instruction Reg

WrAdr

32

Dout

Din

32

ALUop=?

32

Clk

ALU

32

ALU

Control

32

- Every cycle ends AT the next clock tick (storage element updates):
- IR <-- mem[PC] PC<31:0> <-- PC<31:0> + 4

Clk

One “Logic” Clock Cycle

You are here!

PCWr=1

PC

32

MemWr=0

IRWr=1

32

00

32

RAdr

Clk

4

32

Ideal

Memory

Instruction Reg

32

WrAdr

Dout

Din

ALUOp = Add

32

32

Clk

Target

32

0

Mux

0

Mux

1

ALU

0

1

Mux

32

1

ALU

Control

Mux

1

0

<< 2

Extend

16

PCWr

PCWrCond

PCSrc

BrWr

Zero

ALUSelA

IorD

MemWr

IRWr

RegDst

RegWr

1

Mux

32

PC

0

Zero

32

Rs

Ra

32

RAdr

5

32

Rt

Rb

busA

32

Ideal

Memory

32

Instruction Reg

Reg File

5

32

4

Rt

0

Rw

32

WrAdr

32

1

32

Rd

Din

Dout

busW

busB

32

2

32

3

Imm

32

ALUOp

ExtOp

MemtoReg

ALUSelB

Ifetch

ALUOp=Add

1: PCWr, IRWr

x: PCWrCond

RegDst, Mem2R

Others: 0s

Target

32

0

Mux

0

Mux

1

ALU

1

32

ALU

Control

PCWr=1

PCWrCond=x

PCSrc=0

BrWr=0

Zero

ALUSelA=0

IorD=0

MemWr=0

IRWr=1

1

Mux

32

PC

0

Zero

32

32

RAdr

32

busA

Ideal

Memory

32

Instruction Reg

32

4

0

32

WrAdr

32

1

32

Din

Dout

busB

32

2

32

3

ALUSelB=00

ALUOp=Add

Rfetch/Decode

ALUOp=Add

1: BrWr, ExtOp

ALUSelB=10

x: RegDst, PCSrc

IorD, MemtoReg

Others: 0s

Target

32

0

Mux

0

Mux

1

ALU

0

1

Mux

1

ALU

Control

<< 2

Extend

- busA <- Reg[rs] ; busB <- Reg[rt] ;
- Target <- PC + SignExt(Imm16)*4

PCWr=0

PCWrCond=0

PCSrc=x

BrWr=1

Zero

ALUSelA=0

IorD=x

MemWr=0

IRWr=0

RegDst=x

RegWr=0

1

Mux

32

PC

0

Zero

32

Rs

Ra

32

RAdr

5

32

Rt

Rb

busA

32

Ideal

Memory

32

Instruction Reg

Reg File

5

32

4

Rt

0

Rw

32

WrAdr

32

1

32

Rd

32

Din

Dout

busW

busB

32

2

32

3

Control

Beq

Op

Rtype

Imm

6

ALUSelB=10

Ori

Func

Memory

6

16

32

ALUOp=Add

:

ExtOp=1

RExec

1: RegDst

ALUSelA

ALUSelB=01

ALUOp=Rtype

x: PCSrc, IorD

MemtoReg

ExtOp

Target

32

0

Mux

0

Mux

1

ALU

0

1

Mux

1

ALU

Control

Mux

1

0

<< 2

Extend

16

- ALU Output <- busA op busB

PCWr=0

PCWrCond=0

PCSrc=x

BrWr=0

Zero

ALUSelA=1

IorD=x

MemWr=0

IRWr=0

RegDst=1

RegWr=0

1

Mux

32

PC

0

Zero

32

Rs

Ra

32

RAdr

5

32

Rt

Rb

busA

32

Ideal

Memory

32

Instruction Reg

Reg File

5

32

4

Rt

0

Rw

32

WrAdr

32

1

32

Rd

32

Din

Dout

busW

busB

32

2

32

3

Imm

32

ALUOp=Rtype

ExtOp=x

MemtoReg=x

ALUSelB=01

Rfinish

ALUOp=Rtype

1: RegDst, RegWr

ALUselA

ALUSelB=01

x: IorD, PCSrc

ExtOp

Target

32

0

Mux

0

Mux

1

ALU

0

1

Mux

32

1

ALU

Control

Mux

1

0

<< 2

Extend

16

- R[rd] <- ALU Output

PCWr=0

PCWrCond=0

PCSrc=x

BrWr=0

Zero

ALUSelA=1

IorD=x

MemWr=0

IRWr=0

RegDst=1

RegWr=1

1

Mux

32

PC

0

Zero

32

Rs

Ra

32

RAdr

5

32

Rt

Rb

busA

32

Ideal

Memory

32

Instruction Reg

Reg File

5

32

4

Rt

0

Rw

32

WrAdr

32

1

32

Rd

Din

Dout

busW

busB

32

2

32

3

Imm

32

ALUOp=Rtype

ExtOp=x

MemtoReg=0

ALUSelB=01

- Recap
- Review of FSM control
- From Finite State Diagrams to Microprogramming

- Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.
Initial RepresentationFinite State Diagram Microprogram

Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs

Logic RepresentationLogic EquationsTruth Tables

Implementation TechniquePLAROM

“hardwired control”

“microprogrammed control”

Ifetch

Rfetch/Decode

BrComplete

ALUOp=Add

1: PCWr, IRWr

ALUOp=Add

ALUOp=Sub

x: PCWrCond

1: BrWr, ExtOp

ALUSelB=01

RegDst, Mem2R

ALUSelB=10

x: IorD, Mem2Reg

Others: 0s

RegDst, ExtOp

x: RegDst, PCSrc

IorD, MemtoReg

1: PCWrCond

ALUSelA

Others: 0s

PCSrc

RExec

1: RegDst

ALUSelA

ALUOp=Or

ALUSelB=01

1: ALUSelA

ALUOp=Rtype

ALUSelB=11

x: PCSrc, IorD

MemtoReg

x: MemtoReg

ExtOp

IorD, PCSrc

Rfinish

1: ALUSelA

ALUOp=Rtype

ALUOp=Or

RegWr, ExtOp

1: RegDst, RegWr

MemtoReg

x: IorD, PCSrc

ALUselA

ALUSelB=11

ALUSelB=11

ALUSelB=01

ALUOp=Add

1: ALUSelA

x: IorD, PCSrc

x: PCSrc

RegWr

ExtOp

IorD

0

1

8

beq

2

AdrCal

1: ExtOp

ALUSelA

ALUSelB=11

lw or sw

ALUOp=Add

x: MemtoReg

Ori

PCSrc

10

Rtype

lw

sw

OriExec

3

6

5

SWMem

LWmem

1: ExtOp

ALUSelA, IorD

1: ExtOp

MemWr

ALUSelB=11

ALUSelA

ALUOp=Add

ALUSelB=11

x: MemtoReg

ALUOp=Add

PCSrc

x: PCSrc,RegDst

11

MemtoReg

OriFinish

7

4

LWwr

Opcode

O

u

t

p

u

t

s

Control Logic

- Next state number is encoded just like datapath controls

Multicycle

Datapath

Inputs

State Reg

- Alternatively, prior state & condition
- S4, S5, S7, S8, S9, S11 -> State0
- _________________ -> State 1
- _________________ -> State 2
- _________________ -> State 3
- _________________ -> State 4
- State2 & op = sw -> State 5
- _________________ -> State 6
- State 6 -> State 7
- _________________ -> State 8
- State2 & op = jmp -> State 9
- _________________ -> State 10
- State 10 -> State 11

- Next state from current state
- State 0 -> State1
- State 1 -> S2, S6, S8, S10
- State 2 ->__________
- State 3 ->__________
- State 4 ->State 0
- State 5 -> State 0
- State 6 -> State 7
- State 7 -> State 0
- State 8 -> State 0
- State 9-> State 0
- State 10 -> State 11
- State 11 -> State 0

S3

S2

S1

S0

NS3

NS2

NS1

NS0

- Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane

Op5

R = 000000

beq = 000100

lw =100011

sw =101011

ori =001011

jmp =000010

Op4

Op3

Op2

Op1

Op0

0 = 0000

1 = 0001

2 = 0010

3 = 0011

4 = 0100

5 = 0101

6 = 0110

7 = 0111

8 = 1000

9 = 1001

10 = 1010

11 = 1011

S3

S2

S1

S0

NS3

NS2

NS1

NS0

- Each output line the logical OR of logical AND of input lines or their complement: AND minterms specified in top AND plane, OR sums specified in bottom OR plane

lw =100011

sw =101011

R = 000000

ori =001011

beq = 000100

jmp =000010

Op5

Op4

Op3

Op2

Op1

Op0

0 = 0000

1 = 0001

2 = 0010

3 = 0011

4 = 0100

5 = 0101

6 = 0110

7 = 0111

8 = 1000

9 = 1001

10 = 1010

11 = 1011

- Given numbers of FSM, can turn determine next state as function of inputs, including current state
- Turn these into Boolean equations for each bit of the next state lines
- Can implement easily using PLA
- What if many more states, many more conditions?
- What if need to add a state?

- Before Explicit Next State: Next try variation 1 step from right hand side
- Few sequential states in small FSM: suppose added floating point?
- Still need to go to non-sequential states: e.g., state 1 => 2, 6, 8, 10
Initial RepresentationFinite State Diagram Microprogram

Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs

Logic RepresentationLogic EquationsTruth Tables

Implementation TechniquePLAROM

“hardwired control”

“microprogrammed control”

State Reg

Opcode

Control Logic

Multicycle

Datapath

Outputs

Inputs

Types of “branching”

• Set state to 0

• Dispatch (state 1 & 2)

• Use incremented state number

1

Adder

Address Select Logic

State Reg

Opcode

Control Logic

Inputs

Dispatch ROM 1

OpNameState

000000Rtype0110000010jmp1001000100beq1000001011ori1010 100011lw0010101011sw0010

Dispatch ROM 2

OpNameState

100011lw0011101011sw0101

1

Adder

Mux

3

2

1

0

0

Address

Select

Logic

ROM2

ROM1

- Instead of a PLA, use a ROM with one word per state (“Control word”)
State number Control Word Bits 18-2 Control Word Bits 1-0

0 1001010000000100011 1 0000000001001100001 2 0000000000001010010 3 0011000000001010011 4 0011001000001011000 5 0010100000001010000 6 0000000000100010011 7 0000000000100011100 8 0100000010010010000 9 100000010000000000010…1111…00

Initial RepresentationFinite State Diagram Microprogram

Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs

Logic RepresentationLogic EquationsTruth Tables

Implementation TechniquePLAROM

- ROM can be thought of as a sequence of control words
- Control word can be thought of as instruction: “microinstruction”
- Rather than program in binary, use assembly language

“hardwired control”

“microprogrammed control”

- Control is the hard part of processor design
° Datapath is fairly regular and well-organized

° Memory is highly regular

° Control is irregular and global

Microprogramming:

-- A Particular Strategy for Implementing the Control Unit of a

processor by "programming" at the level of register transfer

operations

Microarchitecture:

-- Logical structure and functional capabilities of the hardware as

seen by the microprogrammer

User program

plus Data

this can change!

Main

Memory

ADD

SUB

AND

.

.

.

one of these is

mapped into one

of these

DATA

execution

unit

AND microsequence

e.g., Fetch

Calc Operand Addr

Fetch Operand(s)

Calculate

Save Answer(s)

CPU

control

memory

- Ease of design
- Flexibility
- Easy to adapt to changes in organization, timing, technology
- Can make changes late in design cycle, or even in the field

- Can implement very powerful instruction sets (just more control memory)
- Generality
- Can implement multiple instruction sets on same machine.
- Can tailor instruction set to application.

- Compatibility
- Many organizations, same instruction set

- Costly to implement
- Slow

- Microprogramming and hardwired control have many similarities, perhaps biggest difference is initial representation and ease of change of implementation, with ROM generally being easier than PLA
Initial RepresentationFinite State Diagram Microprogram

Sequencing ControlExplicit Next State Microprogram counter Function + Dispatch ROMs

Logic RepresentationLogic EquationsTruth Tables

Implementation TechniquePLAROM

“hardwired control”

“microprogrammed control”