ECE 6466 “ IC Engineering ” Dr. Wanda Wosik

1. :Silicon VLSI TechnologyFundamentals, Practice and Modelingby J. D. Plummer, M. D. Deal, and P. B. Griffin Chapter 4 Cleaning Processes in Si Technology; cnt’d ECE 6466 “IC Engineering” Dr. Wanda Wosik

2. Models and Simulations Computer Integrated Manufacturing (CIM) Goal:monitor and control machines, recipes to improve YIELDS ! !

3. Modeling Particle Contamination and Yield Contamination Reduction Particles 10nm-10 µm • Particles of feature size cause defects • • ≈ 75% of yield loss in modern VLSI fabs • is due to particle contamination. • • Yield models depend on information • about the distribution of particles. Yields models use measured defect density N(dp) and size (dp) • • Particles on the order of 0.1 - 0.3 µm are • the most troublesome: • • larger particles precipitate easily • • smaller ones coagulate into larger • particles N(dp)=k(dp)-3 (Empirical) Even very small particles lead to failure (pinhole in the oxide ) • Yields are described by Poisson statistics in the simplest case. where AC is the critical area and DO the defect density. • This model assumes independent randomly distributed defects and often underpredicts yields.

4. Yields in ICs • Use of negative binomial NB statistics eliminates these assumptions and is more accurate. Yields depend on defects (D0) density and chip size (Ac) (excluding areas of usual low yields (perimeter) Spacial distribution of defects where C is a measure of the particle spatial distribution (clustering factor). Fraction of failed ITRS needs C ∞ NB P NB - less random/independent (ex. Clustering) • Defects are random and independent • Predicts too low yields

5. Yields in ICs C=2 in all plots Chip size for DRAMs • Vertical lines are estimated chip sizes (from the ITRS). • Note that defect densities will need to be extremely small in the future to achieve the high yields required for economic IC manufacturing. Defect density Negative Binomial Yield = f(DO) ≈40x40mm2 MONITOR DEFECTS Overall yield depends on each step in the manufacturing cycle

6. Modeling Wafer Cleaning • Cleaning involves removing particles, organics (photoresist) and metals from wafer surfaces. • Particles are largely removed by ultrasonic agitation during cleaning. • Organics like photoresists are removed in an O2 plasma or in H2SO4/H2O2 solutions. • The “RCA clean” is used to remove metals and any remaining organics. • Metal cleaning can be understood in terms of the following chemistry. (5) (6) • If we have a water solution with a Si wafer and metal atoms and ions, the stronger reaction will dominate. • Generally (6) is driven to the left and (5) to the right so that SiO2 is formed and M plates out on the wafer. • Good cleaning solutions drive (6) to the right since M+ is soluble and will be desorbed from the wafer surface.

7. Contamination Reduction: Wafer Cleaning Oxidation=removes electrons from an atom Reduction=atoms gain electrons • The strongest oxidants are at the bottom (H2O2 and O3). These reactions go to the left grabbing e- and forcing (6) to the right. • Fundamentally the RCA clean works by using H2O2 as a strong oxidant.

8. Contamination Reduction: Wafer Cleaning No models exist but good understanding of cleaning steps Remove metals by oxidizing (=removing e- -> ions) and by dissolving in cleaning solutions Si+2H2O <->SiO2 +4H++4e- M <-> MZ++ Ze- Reduction<-> oxidation Dominant impurities Stronger oxidants Atoms Ions Take e- from M -> ions are produced Example: In water: SiO2/Si Fe3+/Fe stronger potential Fe3+ -> Fe. Fe is plating on Si, Si is oxidizing • Add H2O2• stronger potential -> H2O2 takes e- from M -> ions soluble in an aqueous sol. H2O2/H2O: will dominate Fe3+/Fe reaction=will take e from Fe  Fe3++ Oxidizes Si Larger negative (stronger) potential -> reaction to the left  all others go to the right  Use OZONE

9. Manufacturing Methods and Equipment Wafer Cleaning High-pH Oxidizes organics -> water soluble compounds and complexes IB IIB and other metals Au, Ag, Cu, Ni, Zn etc. Ex. CuCu(NH3)42+ in SC1 Low-pH Insoluble in NH4OH Al3+, Fe3+

10. Modeling Gettering • • Gettering consists of • 1. Making metal atoms mobile. • 2. Migration of these atoms to • trapping sites. • 3. Trapping of atoms. • • Step 1 generally happens by kicking • out the substitutional atom into an • interstitial site. One possible reaction is: • Step 2 usually happens easily once the • metal is interstitial since most metals • diffuse rapidly in this form. • • Step 3 happens because heavy metals • segregate preferentially to damaged • regions or to N+ regions or pair with • effective getters like P (AuP pairs). • (See text.) • • In intrinsic gettering, the metal atoms • segregate to dislocations around SiO2 • precipitates.

11. Gettering “I” are closer to wafer surface All metal atoms mobile (DMi > DMs 10x) Except of Ti, Mo, etc. DM>> DDopantss Sol. Sol MI>>MS (Cu, Ni) Sol.Sol. MI<<MS (Au, Pt) AuS+IAuikick-out mechanism, then getter AusAui+V dissociative or Frank-Turnbull mech. I increase improves gettering of Au V increase hinders gettering Ex. P diffusion, Ion Implant=damage, intrinsic gettering (=I ) (Fig. 4.8!)

12. Metal Diffusion to the Gettering Sites Long time t Au diffuses to the wafer back side and is trapped Back surface

13. Gettering of Au - the Role of the Back Side Injection of Si-I Metals diffuse much faster than I (silicon) DSi-I >> DDopants I are generated at the back and diffuse -> Aui form, diffuse and get trapped I At high T I -> gettering more effective, not limited by the backside injection I @high P concentrations, Ion Impl., diffusion

14. Trapping the Metal Atoms at the Gettering Sites Trapped by: ion implantation, P diffusion, laser damage, poly-Si films, mechanical damage, etc. But HOW? • *Physical damage -> metal trapped at defect sites; binding energy Eg depends on T; Fraction Bound=(1-K1exp-Eg/kT) • *Segregation, related to solubility in the silicon perfect crystal and in the gettering region • Present in SiCAu,Si=NSiexp(-EA1/kT) CAu,G=NGexp(-EA2/kT) Gettered • -> k0=(CAu,G+CAu,Si)/CAu,Si=1+K2exp-[(EA1-EA2)/kT] --> k0=1+NG/5x1022exp(0.82eV/kT) • k0gives fraction of Au bound in gettered region • *Enhanced sol.sol by high dopant concentrations: in “n” Au=acceptor, “p” - Au=donor • Au+e- Au-, Keq=[Au-]/[Au][e-]=constant, [Au-i]/[Au]ni= [Au-n]/[Au]n or [Au-n]/[Au-i] = n/ni • Au acceptor in “n+” Si (100x if ni(1000°C)=7.14x1018 -> 1021cm-3 doping level) • *Ion pairing model -> AuP less strain (P is small) • * Coulombic attraction Au+P -> Au-P+ • * Interaction with point defects V- in “n+” Aui+V- Aus at the trapepd site • * Intrinsic gettering - trapping on dislocations and SF, which surround precipitates. Dislocations have compressive and tensile stress - accommodate smaller and larger atoms Increases with P concentration

15. Limits and Future Trends in Technology and Modeling; Environment Eliminate defects from wafers: particles, contaminants, clean room -> local=SMIF (standard mechanical interface Wafer cleaning in future ICs-> less chemicals (liquids, vapors), more diluted (disposal) • New cleaning: • Use ozone • Dry and vapor phase, (Vapors, Plasmas) environment! Cluster tools • Low Energy Physical Processes (sputtering) • Photochemically enhanced clean Gettering -> intrinsic (less extrinsic), control Oi, Cs, use low T processing, use modeling tool -> point defects engineering, release, diffuse, entrap. Watch for surface roughness

16. Summary of Key Ideas • A three-tiered approach is used to minimize contamination in wafer processing. • Particle control, wafer cleaning and gettering are some of the "nuts and bolts" of chip manufacturing. • The economic success (i.e. chip yields) of companies manufacturing chips today depends on careful attention to these issues. • Level 1 control - clean factories through air filtration and highly purified chemicals and gases. • Level 2 control - wafer cleaning using basic chemistry to remove unwanted elements from wafer surfaces. • Level 3 control - gettering to collect metal atoms in regions of the wafer far away from active devices. • The bottom line is chip yield. Since "bad" die are manufactured alongside "good" die, increasing yield leads to better profitability in manufacturing chips.