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A Hardware Implementation of the Blowfish Cipher. Michael C.-J. Lin Youn-Long Lin Department of Computer Science Tsing Hua University Hsin-Chu, Taiwan 300, R.O.C. Outline. Introduction Blowfish Algorithm Hardware Architecture Hardware Requirement Conclusion.

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a hardware implementation of the blowfish cipher

A Hardware Implementation of the Blowfish Cipher

Michael C.-J. Lin Youn-Long Lin

Department of Computer Science

Tsing Hua University

Hsin-Chu, Taiwan 300, R.O.C

outline
Outline
  • Introduction
  • Blowfish Algorithm
  • Hardware Architecture
  • Hardware Requirement
  • Conclusion
introduction
Introduction
  • Blowfish Algorithm
    • Block cipher : 64-bit block
    • Variable key length : 32 ~ 448-bit key
    • Unpatented and royalty-free, no license required
  • Hardware Implementation
    • datapath : addition, xor ( 32-bit operand )
    • memory : 4K bytes
blowfish algorithm
Blowfish Algorithm
  • Key expansion + Data encryption
  • Key expansion ( Initialization )
    • key expanded to P array and S box ( total 4148-byte )
    • P array ( P1 ~ P18 : each 32-bit )
    • S box array ( 4-box, each includes S0 ~ S255 , each 32-bit )
  • Data encryption
    • key permutation, key and data substitution
    • only add and xor operation, 32-bit operand
key expansion
Step 1 :

1.expand key to 576-bit

2.xor with P array

3.store results of 2 in P array

Step 2 :

datal = 0x00000000;

datar = 0x00000000;

for (i = 0; i <= 16; i += 2) {

Blowfish_encipher(&datal, &datar);

bf_P[i] = datal;

bf_P[i + 1] = datar;

}

for (i = 0; i <= 3; ++i) {

for (j = 0; j <= 255; j += 2) {

Blowfish_encipher(&datal, &datar);

bf_S[i][j] = datal;

bf_S[i][j + 1] = datar;

}

}

Key expansion

Fig 1. Key Expansion

data encryption
Data encryption

Fig 2. Data Encryption Flow

function f
Function F

Fig 3. Function F

hardware architecture
Hardware Architecture

Fig 4. Chip Specification

Table 1. Mode Spec.

hardware architecture1
Hardware Architecture

Fig 5. Top Module

hardware architecture2
Hardware Architecture
  • e1: Finish loading data from ROM to SRAM
  • e2: Finish initialization and mode != 1
  • e3: Finish encryption and mode != 2
  • e4: Finish decryption and mode != 3

Fig 6. FSM of Controller

hardware architecture3
Hardware Architecture

Fig 8. Blowfish

hardware requirement
Hardware requirement
  • Memory
    • SRAM ( 4K bytes for S box ) : 8 mm2
  • ROM : 4K bytes
    • Random logic : 10K gates
    • ROM compiler : 2mm2
  • Blowfish : 12K gates
    • Datapath : 10K gates
    • Controller : 2K gates
  • Report area : Compass 0.6m cell library
  • Speed predict : 100 MHz
conclusion
Conclusion
  • Key length is variable : 32 ~ 448-bit
  • Suitable application
    • Key doesn’t change often ( ex. Communication link )
  • Compact : only 4K bytes memory
  • Simple operation : addition, xor and table look-up
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