IKI10230 Pengantar Organisasi Komputer Bab 7: Control Unit

1. IKI10230Pengantar Organisasi KomputerBab 7: Control Unit Sumber:1. Hamacher. Computer Organization, ed-5.2. Materi kuliah CS152/1997, UCB. 28 Mei 2003 Bobby Nazief (nazief@cs.ui.ac.id)Qonita Shahab (niet@cs.ui.ac.id) bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/

2. Pengendalian Eksekusi Instruksi: Hardwired Control

3. Computer Processor (active) Memory (passive) (where programs, data live when running) Devices Input Control (“brain”) Datapath (“brawn”) Output Prosesor: Control & Datapath

4. Control lines Instruction Decoder PC Address lines MAR IR Memory bus Data lines MDR R0 Y R(n-1) Add ALU control lines Sub ALU XOR Carry-in TEMP Z Review: Organisasi Prosesor (Single-bus) Control Unit DatapathUnit

5. Instruction IR Control Conditions ADD MARin Control Signals PCout Riin Datapath Interaksi Control  Datapath STEPCONTROL SIGNALS 1. PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin 2. Zout, PCin, WMFC 3. MDRout, IRin 4. R3out, MARin, Read 5. R1out, Yin, WMFC 6. MDRout, Add, Zin 7. Zout, R1in, End

6. Clock Control StepCounter CLK  IR Decoder/Encoder Status Flags   Condition Codes   Control Signals Organisasi Unit Pengendali

7. CLK Clock Reset Control StepCounter  Step Decoder T1 T2Tn   IR Encoder Instruction Decoder LDI Status Flags LD   Condition Codes INSn  Run End Control Signals Pemisahan Decoder & Encoder

8. BR ADD T5 T6 T1   Zin Contoh Struktur Encoder untuk sinyal Zin • Fungsi Logika: Zin = T1 + T6 ADD + T5 BR + … • Zin akan terjadi pada: • T1: untuk setiap instruksi (instruksi berikut: PC+1) • T5: untuk instruksi ADD • T6: untuk instruksi BR

9. ALU PC Clk Interaksi Memori  [Control,Datapath] Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 Registers Next Address Data In B Clk Clk 32 Datapath

10. Pengendalian Eksekusi Instruksi: Microprogrammed Control

11. Microprogramming • Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global Microprogramming: -- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operations Microarchitecture: -- Logical structure and functional capabilities of the hardware as seen by the microprogrammer Historical Note: IBM 360 Series first to distinguish between architecture & organization Same instruction set across wide range of implementations, each with different cost/performance

12. Microinstructions IRin PCin PCout MARin MDRout Yin R1in R1out R3out Zin Zout Clear Y Carry-in Add Read WMFC End STEPCONTROL SIGNALS 1. PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin 2. Zout, PCin, WMFC 3. MDRout, IRin 4. R3out, MARin, Read 5. R1out, Yin, WMFC 6. MDRout, Add, Zin 7. Zout, R1in, End 1 2 3 4 5 6 7

13. IR Starting Address Generator Clock μPC Control Store ControlWord Organisasi Microprogrammed Control Unit IRin PCin PCout MARin MDRout Yin R1in R1out R3out 1 2 3 4 5 6 7

14. IR Starting Address Generator Status Flags Condition Codes Clock μPC Control Store ControlWord Organisasi μProgrammed Control Unit: Branching Addr.Microinstruction 0 PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin 1 Zout, PCin, WMFC 2 MDRout, IRin 3 Branch to starting addr. of appropriate μroutine ……………………………………………………………………………. 25 PCout, Yin, if N=0 then branch to μinstruction 0 26 Offset-field-of-IRout, Add, Zin 27 Zout, R1in, End

15. F4 F3 F2 F1 (4 bits) (4 bits) (3 bits) (3 bits) Encoding of Microinstruction 0000: No transfer 0001: PCout 0010: MDRout 0011: Zout 0100: R0out 0101: R1out 000: No transfer 001: MARin 010: MDRin 011: TEMPin 100: Yin 0000: ADD 0001: SUB . . . 1111: XOR 000: No transfer 001: PCin 010: IRin 011: Zin 100: R0in 101: R1in • Most signals are not needed simultaneously • Many are mutually exclusive: • ALU: 1 function at a time • Data source is unique • Organization: • Vertical Organization (Highly Encoded μInstruction) • Horizontal Organization (otherwise)

16. Microprogram Sequencing: Branching Implementation • 1 Machine Instruction  1 Set of μInstructions • large total number of μInstruction • large Control Store • Many Addressing Modes  many instruction combinations • results in many duplications of common parts • If the common parts are to be shared  many branches • results in longer execution time Need efficient branching techniqe  Bit-ORing

17. Microprogram Sequencing (1/2): Add src,Rdst 000 Start MAR  [PC]; Read; Z  [PC]+1 001 PC  [Z]; WMFC 002 IR  [MDR] 003 Branch[InstDec,OR] Register indirect Indexed Autoincrement Autodecrement 121 141 111 161 MAR  [PC]; Read; Z  [PC]+1 Z  [Rsrc] - 4 MAR  [PC]; Read; Z  [PC]+1 MAR  [Rsrc]; Read 122 142 112 162 PC  [Z]; WMFC MAR, Rsrc  [Z]; Read Z  [Rsrc] Branch[171]; WMFC

18. 170 MAR  [MDR]; Read; WMFC 172 Z  [Y] + [Rdst] 173 171 Y  [MDR] Rdst  [Z] Microprogram Sequencing (2/2): Add src,Rdst Register indirect Indexed Autoincrement Autodecrement 123 143 112 166 Branch[170,OR]; WMFC Branch[170,OR]; WMFC Branch[170,OR]; WMFC Branch[171]; WMFC End

19. Addr.Microinstruction 000 PCout, MARin, Read, Clear Y, Set carry-in, Add, Zin 001 Zout, PCin, WMFC 002 MDRout, IRin 003 μBranch {μPC  101; μPC5,4  [IR10,9]; μPC3  [IR10].[IR9].[IR8]} 121 Rsrcout, MARin, Read, Clear Y, Set carry-in, Add, Zin 122 Zout, Rsrcin 123 μBranch {μPC  170; μPC0  [IR8]}, WMFC 170 MDRout, MARin, Read, WMFC 171 MDRout, Yin 172 Rdstout, Add, Zin 173 Zout, Rdstin, End IR10,9 = 01 (autoincrement) ADD IR8 = 0 (direct) Branching in Microinstruction: Add (Rsrc)+,Rdst Mode Rdst Rsrc 0 1 0 OP code 11 10 8 7 4 3 0 Bit ORing

20. IR Status Flags Condition Codes Decoding Circuits μAR Control Store μIR Next Address μInstruction Decoder  Control Signals Microinstruction Sequencing: Organization

21. F3 F2 F1 F0 (8 bits) (3 bits) (3 bits) (3 bits) F10 F9 F8 . . . (1 bit) (1 bit) (1 bit) Encoding of Microinstruction w/ Next Address 000: No transfer 001: PCout 010: MDRout 011: Zout 100: Rsrcout 101: Rdstout 000: No transfer 001: MARin 010: MDRin 011: TEMPin 100: Yin 000: No transfer 001: PCin 010: IRin 011: Zin 100: Rsrcin 101: Rdstin Address of next microinstruction F4 (4 bits) 0: NextAdrs 1: InstDec 0: No action 1: ORmode 0: No action 1: ORindsrc 0000: ADD 0001: SUB . . 1111: XOR

22. Content of μStore 000 001 002 003 121 122 170 171 172 173

23. /Etc

24. “Macroinstruction” Interpretation User program plus Data this can change! Main Memory ADD SUB AND . . . one of these is mapped into one of these DATA execution unit AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) CPU control memory

25. Control: Hardware vs. Microprogrammed • Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM “hardwired control” “microprogrammed control”