CMOS Digital Integrated Circuits

1. CMOS Digital Integrated Circuits Lec 9 Super Buffer Design

2. Supper Buffer Supper Buffer • Given a large capacitance load Cload • How many stages are needed to minimize the delay? • How to size the inverters? Cload Equiv INV 1 1 N 2 Cg Cd Cd 2Cd NCg Cload Cg 2Cg NCd N:number of inverter stages : optimal stage scale factor

3. Supper Buffer (Cont.) where • Cg: the input capacitance of the first stage inverter. • Cd: the drain capacitance of the first stage inverter. • Each inverter is scaled up by a factor of per stage. • Cload = N+1Cg • All inverters have identical delay of 0(Cd+Cg)/(Cd+Cg)which 0is per gate delay for Equiv INV in ring oscillator circuit with load capacitance = Cg+Cd

4. Supper Buffer Design Equiv INV • Consider N stages, each inverter has same delay 0(Cd+Cg)/(Cd+Cg). Therefore, 1 1 N 2 Cg Cd Cd 2Cd NCg Cload Cg 2Cg NCd d d d d

5. Supper Buffer Design (Cont.) • Goal: Choose  and N to minimize total. • By Cload = N+1Cg, we have • Plug the above equation into total, we get • To minimize total:

6. Supper Buffer Design (Con.) • For the special caseCd=0  ln(opt)=0  opt = e. However, in reality the drain parasitics cannot be ignored. • Example: For Cd=0.5 fF, Cg=1 fF, determine opt and N for Cload= 50pF. opt (ln opt -1) = 0.5  opt = 3.18 The Super Buffer Design which minimizes total for Cload = 50 pF is N=7 Equiv INV stages, and opt = 3.18

7. 1 2 3 V1 V2 V3 Cload,1 Cload,2 Cload,3 CMOS Ring Oscillator Circuit • Oscillation period T is equal to T=PHL1+PLH1+PHL2+PLH2+PHL3+PLL3 =2p+2p+2p =3·2p=6p • For arbitrary odd number (n) of cascade-connected invertes, we have f=1/T=1/(2·n·p) • Also, we can write p=1/(2·n·f)

8. Vout V2 V1 V3 V2 V1 V3 VOH V50% VOL t τPHL2 τPLH3 τPHL1 τPLH2 τPHL3 τPLH1 T Voltage Waveforms of Ring Oscillator