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DØ Silicon Upgrade Issues. Frank Filthaut University of Nijmegen / NIKHEF NIKHEF, 4 August 2000. Run II (a+b+…) Prospects. Accelerator:.

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D silicon upgrade issues

DØ Silicon Upgrade Issues

Frank Filthaut

University of Nijmegen / NIKHEF NIKHEF, 4 August 2000

Run ii a b prospects
Run II (a+b+…) Prospects


  • Initial RunII luminosity estimates pessimistic: should be able to attain luminosities as high as 5·1032 cm-2 s-1 (main limitations: antiproton intensity, proton beam brightness)

  • This should allow for an integrated luminosity of 15 fb-1, provided the accelerator runs another 4 years in Run IIb

  • Note: time of switch to 132 ns operation / crossing angle unclear – but a strong push @FNAL


Run ii a b prospects1
Run II (a+b+…) Prospects


  • Outcome of the RunII Higgs/SUSY Workshop: 15 fb-1/experiment should lead to a large increase in SM Higgs exclusion/evidence limit (180 GeV istd of 115 GeV already reached by LEP2)

The 180 GeV limit is interesting from the point of view of stability of the SM Higgs solution…


D upgrade issues
DØ Upgrade Issues

Run II b accelerator operation presents several problems to the DØ detector:

  • Silicon layers 1, 2 will not survive the anticipated 15 fb-1 integrated luminosity

    • Various scenario’s worked out for silicon temperature during “stand-by” (Tevatron off), maintenance periods

    • Reverse annealing modeled as either 1st-order of 2nd-order process (1st order favoured by data)

    • 50% uncertainty in particle fluence

      In all scenario’s, end up with depletion voltages > 100V (ie. exceeding diode/capacitor breakdown voltages for many detectors)

SVX IIe should survive up to 6 Mrad, ie. perhaps OK for layer 1


D upgrade issues1
DØ Upgrade Issues

  • SIFT chip used to pickup CFT fibre signals for L1 Central Track Trigger does not work in 132 ns mode

    • Actually, it can work but only in a mode which induces too much noise on the SVX front-end (not an option)

      Strictly speaking a problem even before “Run IIb”, but given probability that 132 ns operation will not happen in “Run IIa”, not felt as a big problem

  • Occupancy in two innermost CFT layers  10%  will become useless for pattern recognition, and hence for L1


D upgrade issues2
DØ Upgrade Issues

  • CFT L1,L2 occupancy: way out might be to use stereo fibre layers in trigger (6 layers, forget about inner two)

    • Implies substantial combinatorics  large number of extra connections to be made

    • Additional rejection is lost with increasing luminosity

      Conclusion: 8*axial is better than 6*(axial+stereo)


Silicon upgrade proposals
Silicon Upgrade Proposals

NB: L0  1.5 cm, L5/6  20 cm

  • Minimal:

    • L0: SS, sp =25 m, rp = 25 or 50 m, ladders 6 or 12 cm long

    • L1/2: SS glued back to back (20), 6 barrels as in R2a

  • Pixel:

    • L0/1: ATLAS-style pixels, 50*400 m. Length?

    • L2: SS glued back to back (20)

  • IRIS:

    • L1: SS axial, sp =25 m, rp = 50 m, 200 m thick (or DS 900?)

    • L2: SS glued back to back (20) (same parameters)

    • L5/6 (“ISL” à la CDF): SS, rp=150 m axial, 390 m (900) glued back to back. 18 modules/layer, each 4*40 cm long

    • “Integrate” with idea for inclusion of stereo fibres in L1CTT

  • Full:

    • L0-2: SS axial (pitch?)

    • L3-5: SS glued back to back (20), ladders 10 or 15 cm long

  • Simulation studies (GEANT) starting:

    • Intermediate strips?

    • Strip length

    • Material distribution


Silicon upgrade issues
Silicon Upgrade Issues

  • Present design (featuring 5 detector types, 9 HDI types, lot of manual steps) very time-consuming

    • more automisation would greatly facilitate project

  • Foresee 9-month shutdown period  March 2003

    • Enough time to dis-assemble present detector in case of partial replacement (how to keep silicon cooled)?

  • In all but the minimal upgrade scenario’s, need new readout chip

    • Less than 2000 SVX IIe on the shelf, 1.2 m technology being abandoned

    • Also SVX III chip currently in use by CDF (0.8 m) will be obsolete (also much more expensive)

    • CDF interested in joint effort towards SVX IV development (start by down-scaling from SVX III)

      • strong push from Lab

      • nevertheless schedule risk

      • significantly more control lines than SVX IIe  investigate built-in decoder?

      • Need new DAQ

    • APV25 (CMS): seems to work, but analogue  need separate ADC; also DAQ change

  • Even now, pattern recognition is less redundant than desirable – can one do better?

  • “Dislike” of disks –implications for forward tracking?

  • Anticipate shorter interaction region due to crossing angle (loss in luminosity)?


Dutch thoughts
Dutch Thoughts…

  • None of the current scenario’s seems to have a satisfactory solution for the CFT innermost layers’ occupancy problem

  • The most straightforward solution to this is to replace these innermost layers with silicon

    • One should be able to trigger on the information coming from this silicon

    • Rely on SIFT replacement – we’re as good as dead anyway if this problem isn’t solved

    • Replacement with 3 layers (instead of 2) would lead to more redundant system

    • Cooling needs attention

      • SVX + SIFT chips

      • Silicon itself needs cooling, if inner layers are to survive full Run IIb (“quick” replacement??)

    • Oxygenated silicon

  • Instead of having various independent projects, try to make integrated design (going from L0/1 to L5/6)

    • Uniform design should gain a lot of development/ production time

  • Not much thought given yet to detector types (SS, DS, SS glued back to back)

(NIKHEF DØ group, Marcel Demarteau, Ron Lipton, Harry Weerts, Marvin Johnson)