Timing analysis
This presentation is the property of its rightful owner.
Sponsored Links
1 / 15

Timing Analysis PowerPoint PPT Presentation


  • 104 Views
  • Uploaded on
  • Presentation posted in: General

ECE 545 Lecture 8a. Timing Analysis. R equired reading. P. Chu, RTL Hardware Design using VHDL Chapter 8.6 Timing Analysis of a Synchronous Sequential Circuit Chapter 16.1 Overview of a Clock Distribution Network Chapter 16.2 Timing Analysis with Clock Skew. Hold & Setup Time

Download Presentation

Timing Analysis

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


Timing analysis

ECE 545

Lecture 8a

Timing Analysis


R equired reading

Required reading

  • P. Chu, RTL Hardware Design using VHDL

    • Chapter 8.6 Timing Analysis of a Synchronous

    • Sequential Circuit

    • Chapter 16.1 Overview of a Clock Distribution

    • Network

    • Chapter 16.2 Timing Analysis with Clock Skew


Timing analysis

Hold & Setup Time

Metastability

ECE 448 – FPGA and ASIC Design with VHDL


Violation of hold or setup time

Violation of Hold or Setup Time


Response of a flip flop to timing violation

Response of a Flip-Flop to Timing Violation

There exists a third and unstable point of equilibrium

between the two stable states representing

the binary states 0 and 1 respectively.


Points of equilibrium in flip flops and latches

Points of Equilibrium in Flip-Flops and Latches


Patterns of metastable behavior

Patterns of Metastable Behavior


Response to timing violation

Response to Timing Violation


Impact on downstream circuitry

Impact on Downstream Circuitry


Timing analysis

Clock Skew

ECE 448 – FPGA and ASIC Design with VHDL


Clock skew

Clock Skew


Clock skew map for a cell processor

Clock Skew Map for a Cell Processor


Incorrect clock tree layout narrow meander

Incorrect Clock Tree Layout – Narrow Meander


Optimized clock tree layout h tree

Optimized Clock Tree Layout – H Tree


Clock skew summary

Clock Skew - Summary


  • Login