Timing analysis
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ECE 545 Lecture 8a. Timing Analysis. R equired reading. P. Chu, RTL Hardware Design using VHDL Chapter 8.6 Timing Analysis of a Synchronous Sequential Circuit Chapter 16.1 Overview of a Clock Distribution Network Chapter 16.2 Timing Analysis with Clock Skew. Hold & Setup Time

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Timing Analysis

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ECE 545

Lecture 8a

Timing Analysis


Required reading

  • P. Chu, RTL Hardware Design using VHDL

    • Chapter 8.6 Timing Analysis of a Synchronous

    • Sequential Circuit

    • Chapter 16.1 Overview of a Clock Distribution

    • Network

    • Chapter 16.2 Timing Analysis with Clock Skew


Hold & Setup Time

Metastability

ECE 448 – FPGA and ASIC Design with VHDL


Violation of Hold or Setup Time


Response of a Flip-Flop to Timing Violation

There exists a third and unstable point of equilibrium

between the two stable states representing

the binary states 0 and 1 respectively.


Points of Equilibrium in Flip-Flops and Latches


Patterns of Metastable Behavior


Response to Timing Violation


Impact on Downstream Circuitry


Clock Skew

ECE 448 – FPGA and ASIC Design with VHDL


Clock Skew


Clock Skew Map for a Cell Processor


Incorrect Clock Tree Layout – Narrow Meander


Optimized Clock Tree Layout – H Tree


Clock Skew - Summary


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