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ECE 448: Spring 13 Lab 3 Sequential Logic for Synthesis Simulation using ModelSim. Agenda for today. Part 1: Introduction to Lab 3 Top-level circuit LFSR MISR Debouncer Edge Detector Part 2: Hands-on Session: Simulation Using ModelSim Part 3: Demos of Lab 2. Part 1.

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ECE 448: Spring 13

Lab 3

Sequential Logic for Synthesis

Simulation using ModelSim


Agenda for today

  • Part 1: Introduction to Lab 3

    • Top-level circuit

    • LFSR

    • MISR

    • Debouncer

    • Edge Detector

  • Part 2: Hands-on Session:

  • Simulation Using ModelSim

  • Part 3: Demos of Lab 2


Part 1

Introduction to Lab 3

ECE 448 – FPGA and ASIC Design with VHDL



step

run

loadA

IVA

loadB

IVB

loadA

loadB

8

8

OR

cnz

en

en

nexti

nexti

ld

ld

OR

OR

LFSR

LFSR

next

clk

clk

rst

rst

rst

rst

clk

clk

AND

not done

AND

X”00”

X”00”

8

8

en

CNTR

UP

next

0

0

1

1

rst

rst

cnz

cnz

clk

clk

8

8

k

10

A

B

= X”3FF”

10

k9..8

sel

2

8

done

k7..0

LAB2

≠ 0

En

‘0’

cnz

X

Y

8

8

en

next

en

next

rst

rst

rst

MISR

rst

MISR

clk

clk

clk

clk

8

8

XSGN

YSGN


Source of Inputs & Display of Outputs

(to be experimentally tested in Lab 4)

Used to display

XSGN, YSGN

Used to enter

IVA, IVB

Used to generate

loadA, loadB,

step, run



Generation of Inputs Using Buttons

RESET

rst

rst

rst

rst

rst

rst

rst

rst

BTNL

loadA

Debouncer

RED

clk

clk

clk

clk

clk

clk

clk

BTNR

loadB

Debouncer

RED

BTNU

step

Debouncer

RED

rst

run

rst

‘1’

Q

D

BTNS

en

Debouncer

RED

clk

clk

RED = Rising Edge Detector


Pseudo-Random Number Generators

Implemented Using LFSRs


PRNG

  • Generates a sequence of numbers that approximates the properties of random numbers.

  • The sequence is fully deterministic, i.e., it can

    be repeated based on an initial state of PRNG.

  • The period of the sequence may be made very large (typically, 2n-1, where n is an internal state size)


PRNG

  • Random Numbers are often important

    • Testing of VLSI circuits

    • Cryptography

    • Monte Carlo simulations

    • Noise addition

    • Bit error detection,

      and many other applications


Linear Feedback Shift Register (LFSR)

Each stage = D flip-flop

 L, C(D) 

Length

Connection polynomial, C(D)

C(D) = 1 + c1D + c2D2 + . . . + cLDL


Sj-1

Sj-2

Sj-(L-1)

Sj-L

Initial state

[sL-1, sL-2, . . . , s1, s0]

LSFR recursion:

sj = c1sj-1 c2sj-2 . . .  cL-1sj-(L-1) cLsj-L

for j  L


Example of LFSR

 4, 1+D+D4

Length

Connection polynomial, C(D)

C(D) = 1 + 1D + 0D2 + 0D3 +1D4

c1=1

c2=0

c4=1

c3=0


LFSR State Sequence

s4

s3

s2

s1

s0

s4 = c1s3c2s2 c3s1  c4s0 = s3 s0


LFSR to be used in Lab 3

 8, 1+D4+D5+D6+D8

Length

Connection polynomial, C(D)

Selected to make a period = 28-1 = 255


Initializing serial shift register w ith parallel load

D

D

D

D

Q

Q

Q

Q

Initializing Serial Shift Register with Parallel Load

Load

D(3)

D(2)

D(1)

D(0)

Sin

Clock

Enable

Q(3)

Q(2)

Q(1)

Q(0)

Hint: Use similar technique for initializing LFSR



MISR - Multiple Input Signature Register

D7

D6

D5

D4

D3

D2

D1

D0

rst

rst

rst

rst

rst

rst

rst

rst

rst

rst

rst

rst

rst

rst

rst

rst

D

D

D

D

D

D

D

D

Q

Q

Q

Q

Q

Q

Q

Q

en

en

en

en

en

en

en

en

en

Q7

en

Q6

en

Q5

en

Q4

en

Q3

en

Q2

en

Q1

en

Q0

AND

AND

AND

AND

AND

AND

AND

AND

C7

C6

C5

C4

C3

C2

C1

C0

MISR is used to compress multiple inputs D

to a single signature Q

C=C7..C0 should be declared as a generic in VHDL code

For the purpose of testing set C=X”B8”



Debouncer
Debouncer

Capacitance in the button and contacts “bouncing” causes spurs that cause false positives.

A debouncing circuit removes these spurs.

This graphs shows releasing a button.


Debouncer1
Debouncer

When the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually in the order of ms.


Debouncer2
Debouncer

Debouncer

reset

output

input

clk




Rising edge detector red
Rising Edge Detector - RED

  • Turn a step function into an impulse

  • Allows a step to run a circuit for only one clock cycle

Rising Edge Detector


Rising edge detector
Rising Edge Detector

reset

rising edge detector

input

output

clk

clk

input

output


Part 2

Hands-on Session

Simulation Using ModelSim

ECE 448 – FPGA and ASIC Design with VHDL


Hands-on Session

on ModelSim using

four_bit_counter

based on JK flip-flops


Part 3

Lab 2 Demos

ECE 448 – FPGA and ASIC Design with VHDL


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