The amd k8 processor architecture
Download
1 / 12

The AMD K8 Processor Architecture - PowerPoint PPT Presentation


  • 176 Views
  • Uploaded on

The AMD K8 Processor Architecture. December 14 th 2006. K7 vs K8. K7: 3 x86 decoding units, 3 integer units (ALU), 3 floating point units (FPU),128KB L1 cache K8: 3 decoders (16 bytes of instructions per clock cycle); x86 instructions decoded into fixed length micro-operations (µOPs).

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about ' The AMD K8 Processor Architecture' - portia-gill


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

K7 vs k8
K7 vs K8

K7: 3 x86 decoding units, 3 integer units (ALU), 3 floating point units (FPU),128KB L1 cache

K8: 3 decoders (16 bytes of instructions per clock cycle);

  • x86 instructions decoded into fixed length micro-operations (µOPs).

  • Complex instructions are decoded into 2 + µOps

  • FastPath: Certain µOPs are packed together

  • µOPs are then dispatched to the execution units.

  • 3 Address Generation Units (AGU) for Loads and Stores

  • Three integer units (ALU): most µOps executed in one cycle, multiplication has a 3 cycles latency in 32 bits, and a 5 cycles latency in 64 bits

  • Three floating point units (FPU), that handle x87, MMX, 3DNow!, SSE and SSE2 instructions

  • Load/Store stage: The L1 is dual-ported, that means it can handle two 64 bits reads or writes each clock cycle




K8 l1 and l2cache
K8 L1 and L2Cache

The L1 cache

The L2 cache






ad