TELL1

1. ODIN CCPC TELL1 Arx TTCrx Arx GBC Arx CCPC Arx Repeater board Control Board Buff Buff TTCrx LV ECS SPECS Buff Buff Temperature Board ELMB Trigger Logic Electronics Cage TTC LBH8LXCO01 LBH8LX01 LBH8LX02 Analog Cable 60m Ethernet (data) Ethernet (control) 6 SPECS Control Cable 20m 64 LBH8WICO01 ISeg HV PS LV PS Beam Zone CAN VELO Testbeam setup Temperature interlock CAN JC Wang Counting room LBTBXP02

2. Testbeam Computing • One credit card PC (CCPC) on each TELL1. Scripts in tcsh are created to automatically login and start relevant processes to deliver zero suppressed (ZS) or NZS data. • One CCPC on readout supervisor (Odin) board also runs process for trigger and time control. • 3 Linux boxes (4-CPU 2.8 GHz, 2GB RAM): 1 for DAQ control and data analysis, 2 for event building. Scripts to increment run number and write data into designated locations. • 2 Window PCs: 1 is SPECS master to communicate with control board, and also read temperature board via CAN bus. The other control Iseg HV via CAN bus. Either one can be PVSS master to control various processes. • Data are written to 3 200-GB disks, and copied to castor storage server by a cron job every 10 minutes. JC Wang

3. Beam Profile • Only a quarter of each hybrid is readout. • The beam is tuned to spread out and cover the whole quarter. Facing beam JC Wang

4. JC Wang

5. 19R vs 18R 19f vs 18f 19f vs 20f 19R vs 20R Strip electronics ID Correlation Stereo phi strips JC Wang

6. Noise Performance 1 ADC count ~ 720 e. MP charge of 1 MIP in 200 mm Si ~ 16000 e ~ 22 ADC. MP charge of 1 MIP in 300 mm Si ~ 24000 e ~ 33 ADC. S/N (300mm) ~ 33 / (1.7-2.0) CM subtracted noise (ADC counts) JC Wang Channel ID

7. Charge Distribution Pedestal Subtracted ADC Readout JC Wang Channel ID ADC Readout

8. Number of Clusters with Interaction Setup ~15% TELL1 FPGA clustering algorithm has flaw Number of Clusters JC Wang

9. Data Sets We Took • Latency and signal shape sampling delay. • Bias HV scan on all hybrids at normal incidence, plus M18R HV scan at -10 degree. • Track at different angle: 0, 5, 10, 16, -10 degrees. • Electronics bias scan: vfp, vfs, prebias, ibuf, and compare with Heidelburg setting. • Several versions of FPGA code. • Different trigger rates. • Grounding. • Interaction events. • … JC Wang

10. What is next? • Grounding test needs to be finished. • Analysis of data is already started. • We need NZS to ZS preprocessor, existing ZS data need to be reprocessed too. • Most of analysis work need to be done before Nov beam test. • Prepare for Nov beamtest. JC Wang

11. H8 JC Wang

12. A0 A1 B1 A2 A0 T T T T T B2 A1 Trigger count 4 ns width A2 gate NIM-ECL translator B1 Enable B2 CK Trigger out 40 MHz L0 Scintillation Trigger (II) JC Wang

13. Significant Issues • Mod19R has crack on Q4, difficult to apply HV. Dark current > 10 mA. Miraculasly it worked. • Temperature board has certain port (total 64) that causes CAN readout crashes. • Analog power fuse on TELL1 22 was bad. • Several Arx boards have bad ADCs. • Electronics channel to strip map is not taken in TELL1 FPGA, resulting wrong clustering. • Clock latency mystery. • Data file contains both ZS and NZS banks can was not able to be analyzed by VETRA. • …… JC Wang

14. Channel Correlation with Interaction Setup JC Wang