Functional Test Generation using Constraint Logic Programming

1. Functional Test Generationusing Constraint Logic Programming Zhihong Zeng, Maciej Ciesielski Dept. of Electrical & Comp. Engineering University of Massachusetts, Amherst Bruno Rouzeyre LIRMM, Université de Montpellier II

2. Outline • Introduction • Functional test generation for design validation • Related work on satisfiability (SAT) • Boolean and hybrid approaches to SAT • New word-level SAT solver • Unified Boolean and arithmetic domains • Based on Constraint Logic Programming • Experimental results, conclusions VLSI-SOC 2001

3. Functional Simulation • A viable approach to design validation • Scales well with design size • Predictable run time • The way engineer thinks • Downsides • Incomplete, low “functional” coverage • Confidence: when am I done? (coverage metrics are used to help) VLSI-SOC 2001

4. Functional Validation - typical scenario 100 % ? 100.0 Deterministic tests Normalized verification test cycles 80 % Coverage Pseudo-random directed tests 1.0 50 % Manual directed tests Test development time VLSI-SOC 2001

5. Deterministic Testing-Automation • Functional test generation • Given an RTL design and a coverage metric • Goal: generate test vectors to reach predefined coverage goal • Coverage metrics: • code coverage, • state coverage, • transition coverage, etc • Formulate as satisfiability (SAT) problem VLSI-SOC 2001

6. Our Design Validation Framework Simulation Seed Environment Symbolic Simulation (bounded time model) Y Next Simulation Target N Convert to a SAT Problem Done Word-level SAT BDDs Boolean SAT VLSI-SOC 2001

7. A D + B 0 F 1 E s C * x Formulating a SAT Problem Test vector Simulation target (value to be satisfied) 1 1 0 0 1 1 1 0 1 state=s3 F= b’0110 F> d’12 Symbolic expression to be satisfied VLSI-SOC 2001

8. Design Validation of RTL Designs • Behavioral or RT-level designscontain datapath and control logic • Word-level arithmetic operators • Boolean logic • Previous approaches are not efficient • Gate-level ATPG, Boolean SAT, BDDs – bit-level • Word-level information is not utilized • Need more abstract, word-level models VLSI-SOC 2001

9. Previous Work - Boolean SAT • Based on Davis-Putnam procedure • Tools: SATO, RelSat, GRASP, Chaff, … • Conflict-based non-chronological back-jumping • Conflict-based learning • Variable ordering • Restart • Careful implementation • BDD-based SAT WORD-LEVEL information is ignored! VLSI-SOC 2001

10. Previous Work - Hybrid SAT • HSAT: [Fallah et al. DAC’98] • CNF-based SAT to solve Boolean constraints • Linear Programming relaxation to check consistency of arithmetic constraints • ATPG + Arithmetic solver [Huang et al. DAC’00] • Gate-level ATPG to justify objectives in Boolean domain • Modular arithmetic solver to solve arithmetic constraints • Word-level implications between two domains are attempted: weak, not robust VLSI-SOC 2001

11. 12>A b k A3B+C f g h j b 0 a=1 B>C C>1 1 L K A<4C  Arithmetic solver: infeasible  Conflict, backtrack Hybrid Approaches - Limitations • Inefficient constraint propagation across domains: Boolean/arithmetic  f=1, g=1 h=1, j=1 VLSI-SOC 2001

12. 12>A b 0 A3B+C f g h j b a=1 Boolean to Arithmetic B>C C>1 L K A<4C Constraint Propagation – a Problem • A better constraint propagation: tighter interaction between the two domains f=1, g=1 h=1, j=1 A=11,C=2 Arithmetic to Boolean k=0 VLSI-SOC 2001

13. Our approach:Word-level SAT in a unified domain • Put arithmetic and Boolean constraints in same domain • Constraint propagation is implicit to one engine • More efficient than hybrid approach • Use the state-of-the-art constraint solving techniques • No need to develop your own Branch & Bound procedure • Constraint solving is extensively researched by AI, CS • Our previous work • LPSAT: SAT based on Linear Programming • A new word-level SAT • Based on constraint logic programming (CLP-SAT) VLSI-SOC 2001

14. Why Another Unified Approach? • LPSAT [DATE’01]: SAT based on ILP • Non-linear constraints must be linearized • Numerical convergence problem (integers) • Optimization engine CPLEX ($$, not a SAT solver) • Alternative: SAT based on Constraint Logic Programming (CLP-SAT) VLSI-SOC 2001

15. CLP-SAT:SAT using Constraint Logic Programming • Use Gnu-prolog as solving engine • Publicly available • Constraint solving over finite domain • A native Prolog compiler: fast execution time • Modeling is straightforward • No need to linearize complex operators (MPY) • Built-in predicates for Boolean gates VLSI-SOC 2001

16. A D + < B s E * X 1 C Z 0 Y Design/Constraint Modeling • Identify Arithmetic and Boolean domains • Word-level signals: B, D, E, X, Z • (Partial) bit expansion: A, C, Y Y = Y[0] + 2*Y[1] + 4*Y[2] + … • Single-bit Boolean signals: s VLSI-SOC 2001

17. CLP-SAT – Modeling the Constraints VLSI-SOC 2001

18. 9 16 D A + 16 8 B Z A+B = Z + D*28 D <= 29 Z <= 28 Handling Modular Arithmetic • A 16-bit adder: Z = A + B Z <= 28 Z = (A+B) mod 256 ? • Adding a free variable, D VLSI-SOC 2001

19. AH > 28-bit BH s == 28-bit s A > 56-bit B > 28-bit AL BL Handling Wide Arithmetic Operators • Internal representation (computer): 32-bit words • Largest domain in CLP is 28-bit • Decompose using Boolean logic VLSI-SOC 2001

20. Experiments - Benchmarks • M13 – 13-bit multipliers (sat, non) • M16 – 16-bit multipliers, decomposed (sat, non) • Square - compute Z2 = X2 + Y2, 16-bit variables • Quadratic - solve X2 = a X + b for16-bit X • Linear-k - k-wide chain of comparators (k=40, 90), simple structure, large # inputs (over 1200) • GCD-k - sequential circuit, 24-bit gcd unrolled k=20, 40 time frames • Mdpe - multiplier feeding a dynamic priority encoder, taken from realistic design VLSI-SOC 2001

21. Benchmarks - Statistics VLSI-SOC 2001

22. Experimental Results Run-time speed-up *:real CPU time VLSI-SOC 2001

23. Conclusions • Functional test generation for design validation • Symbolic simulation + word-level SAT • A new word-level SAT in a unified domain • Based on constraint logic programming • A good alternative to LPSAT • Use the state-of-the-art constraint solving techniques • Preliminary results are promising: • Good for mixed arithmetic and Boolean logic • Limitation: not competitive for designs with large portions of random logic VLSI-SOC 2001