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LOGIC DESIGN First Year - Computer Eng. Dept.

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LOGIC DESIGNFirst Year - Computer Eng. Dept.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Text book: M. Morris Mano, “ Digital Design” , third edition, Prentice Hall, 2002

- References:
- M. Mano and C. R. Kime , “Logic and Computer Design Fundamentals”, Prentice
- Hall, 2000.
- Daniel Gajski, “Principles of Digital Design”, Prentice Hall, 1997.

Cairo University

Faculty of Engineering

Computer Engineering Department

Introduction to Logic Design

Sunday/Thursday –2007/2008

Course Description:

Digital Logic Design, The nature of digital logic, numbering system, Boolean algebra, karnaugh maps, decision –making elements, memory elements, latches, flip-flops, design of combinational and sequential circuits, integrated circuits and logic families, shift registers, counters and combinational circuits, adders, substraters ,multiplication and division circuits, memory types. Exposure to logic design automation software.

Credit: This course consists of 1 1 /2 lectures per week

Dr. Ihab Talkhan

Instructor(s): Dr. Ihab E. Talkhan

This course is designed to introduce the student to the basic techniques of design and analysis of digital circuits

Dr. Ihab Talkhan

Course contents:

- Grading:60% (2 tests - no make-ups)
- 15% Attendance
- 25% Assignments (all assignments from the text book, end of chapter selected problems)
- Testing dates:to be announced later
- Final test date:refer to First term Schedule
- Assistant: to be announced later
- Office hours: to be announced later

Dr. Ihab Talkhan

Design Cycle

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Hardware & Micro-program method

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Various binary systems suitable for representing information in digital components [ decimal & Alphanumeric].
- Digital system has a property of manipulating discrete elements of information, discrete information is contained in any set that is restricted to a finite number of elements, e.g. 10 decimal digits, the 26 letters of the alphabet, 25 playing cards, and other discrete quantities.

Dr. Ihab Talkhan

- Early digital computers were used mostly for numeric computations, in this case the discrete elements used were the digits, from which the term digital computer has emerged.
- Discrete elements of information are represented in a digital system by physical quantities called signal [voltages & currents] which have only two discrete values and are said to be binary.

Dr. Ihab Talkhan

Voltage

5

Logic – 1 range

2

Intermediate region, crossed only during state transition

Transition , occurs between the two limits

0.8

Logic – 0 range

0

time

- Electrical Signals [ voltages or currents ] that exist throughout a digital system is in either of two recognizable values [ logic-1 or logic 0 ]

Dr. Ihab Talkhan

- Digital computers use the binary number system that has two digits “0” and “1”, a binary digit is called a “bit”, thus information is represented in digital computers in groups of bits.
- By using various coding technique, groups of bits can be made to represent not only binary numbers but also any other group of discrete symbols.
- To simulate a process in a digital computer, the quantities must be quantized, i.e. a process whose variables are presented by continuous real-time signals needs its signals to be quantized using an analog-to-digital (A/D) conversion device.

Dr. Ihab Talkhan

- The memory unit: stores programs, inputs, outputs and other intermediate data.
- The processor unit: performs arithmetic and other data-processing operations as specified by the program.
- The control unit: supervises the flow of information between the various units. It also retrieves the instructions, one by one, from the program stored in memory and informs the processor to execute them

Dr. Ihab Talkhan

- A CPU enclosed in a small integrated circuit package is called a microprocessor.
- The program and data prepared by the user are transferred into the memory unit by means of an input devices such as a keyboard.
- An output device, such as a printer, receives the results of the computations and the printed results are presented to the user.

Dr. Ihab Talkhan

- A number is base “r” contains r digits 0,1,2,…..(r-1) and is expressed with a power series in “r”.
- A number can also be expressed by a string of coefficients [positional notation].

Least significant digit

Most significant digit

Radix point

Dr. Ihab Talkhan

- The Aicoefficients contain “r” digits, and the subscript “ i ” gives the position of the coefficient, hence the weight riby which the coefficient must be multiplied.
- To distinguish between numbers of different bases, we enclose the coefficients in parentheses and place a subscript after the right parenthesis to indicate the base of the number.

Dr. Ihab Talkhan

- The decimal number system is of base or radix r = 10, because the coefficients are multiplied by powers of 10 and the system uses ten distinct digits [0,1,2,…9].
- Decimal number is represented by a string of digits, each digit position has an associated value of an integer raised to the power of 10.
- Consider the number (724.5)10

Dr. Ihab Talkhan

- To convert any numbering system to decimal, you expand the number to a power series with its base.
- Example:
- Convert (312.4)5 to its equivalent decimal, note that the number is in base 5.

Conversion from base 5 number to its equivalent decimal number

Radix 5

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Converting a Binary number to its equivalent Decimal:
(11010.11)2

Note that, when a bit is equal to “0”, it does not contribute to the sum during the conversion. Therefore, the conversion to decimal can be obtained by adding the numbers with powers of two corresponding to the bits that are equal to “1’.

Dr. Ihab Talkhan

- 210 = 1024 is referred to as Kilo “K”
- 220 = 1,048,567 is referred to as Mega “M”
- 230 is referred to as Giga “G”
- Example: 16M = 224 = 16,777,216

Dr. Ihab Talkhan

- The conversion of a decimal number to binary is achieved by a method that successively subtracts powers of two from the decimal number, i.e. it is required to find the greatest number (power of two) that can be subtracted from the decimal number and produce a positive difference and repeating the same procedure on the obtained number till the difference is zero.

Dr. Ihab Talkhan

- Find the binary equivalent of (625)10
- 625 – 512 = 113512 = 29
- 113 – 64 = 49 64 = 26
- 49 – 32 = 17 32 = 25
- 17 – 16 = 1 16 = 24
- 1 – 1 = 0 1 = 20

- (625)10 = 29 + 26 + 25 + 24 + 20 = (1001110001)

LSB

MSB

Position 10

Dr. Ihab Talkhan

- If the number includes a radix point, it is necessary to separate it into an integer part and a fraction part, since each part must be converted differently.
- The conversion of a decimal integer to a number in base “r“ is done by dividing the number and all successive quotients by “ r “ and accumulating the remainders.
- The conversion of a decimal fraction to base “ r “ is accomplished by a method similar to that used for integer, except that multiplication by “ r “ is used instead of division, and integers are accumulated instead of remainders.

Dr. Ihab Talkhan

- Find the binary equivalent of (41.6875)10
- Separate the number into an integer part & a fraction part.

Integer Part:

Fraction Part:

Integer

remainder

MSB

LSB

LSB

MSB

( .6875)10 = ( .1011)2

Thus: (41.6875)10L (101001.1011)2

(41)10 = (101001)2

Dr. Ihab Talkhan

- The process of multiplying fractions by “ r “ does not necessarily end with zero, so we must stop at a certain accuracy , i.e. number of fraction digits, otherwise this process might go forever.

Dr. Ihab Talkhan

- Octal number system is a base 8 system with eight digits [ 0,1,2,3,4,5,6,7 ].
- To find the equivalent decimal value, we expand the number in a power series with a base of “ 8 ”.
- Example:
- (127.4)8 = 1 x 82 + 2 x 81 + 7 x 80 + 4 x 8-1
= (87.5)10

- (127.4)8 = 1 x 82 + 2 x 81 + 7 x 80 + 4 x 8-1

Dr. Ihab Talkhan

- The Hexadecimal number system is a base 16 system with the first ten digits borrowed from the decimal system and the letters A,B,C,D,E,F are used for digits 10,11,12,13,14 and 15 respectively.
- To find the equivalent decimal value, we expand the number in a power series with a base of “ 16 ”.
- Example:
- (B65F)16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160
= (46687)10

- (B65F)16 = 11 x 163 + 6 x 162 + 5 x 161 + 15 x 160

Dr. Ihab Talkhan

- It is customary to borrow the needed “ r “ digits for the coefficients from the decimal system, when the base of the numbering system is less than 10.
- The letters of the alphabet are used to supplement the digits when the base of the number is greater than 10.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- The Octal & Hexadecimal systems are useful for representing binary quantities indirectly because they posses the property that their bases are powers of “2”.
- Octal base = 8 = 23 & Hexadecimal base = 16 = 24, from which we conclude:
- Each Octal digit correspond to three binary digits
- Each Hexadecimal digit correspond to four binary digits.

Dr. Ihab Talkhan

- The conversion from Binary to either Octal or Hexadecimal is accomplished by partitioning the Binary number into groups of three or four digits each respectively, starting from the binary point and proceeding to the left and to the right. Then, the corresponding Octal or Hexadecimal is assigned to each group.
- Note that, 0’s can be freely added to the left or right to the Binary number to make the total number of bits a multiple of three or four.

Dr. Ihab Talkhan

- Find the Octal equivalent of the Binary number:
( 10110001101011.11110000011)2

010 110 001 101 011 . 111 100 000 110

2 6 1 5 3 7 4 0 6

(010110001101011.111100000110)2 L(26153.7406)8

Added “0’s”

Dr. Ihab Talkhan

- Find the Hexadecimal equivalent of the Binary number:
( 10110001101011.11110000011)2

0010 1100 0110 1011 . 1111 0000 0110

2 C 6 B F 0 6

(10110001101011.11110000011)2 L(2C6B.F06)16

Added “0’s”

Dr. Ihab Talkhan

- Conversion from Octal or Hexadecimal to Binary is done by a procedure reverse to the previous one.
- Each Octal digit is converted to a three-digit binary equivalent.
- Each Hexadecimal digit is converted to its four-digit binary equivalent.

Dr. Ihab Talkhan

- Find the Binary equivalent of (673.12)8
6 7 3 . 1 2

110 111 011 001 010

(673.12)8 = (110111011.001010)2

Dr. Ihab Talkhan

- Find the Binary equivalent of (3A6.C)16
3 A 6 . C

0011 1010 0110 1100

(3A6.C)16 = (110111011.001010)2

Dr. Ihab Talkhan

- The Octal or Hexadecimal equivalent representation is more convenient because the number can be expressed more compactly with a third or fourth of the number of digits.

Dr. Ihab Talkhan

Carry

Two digits

Arithmetic 1 + 1 = 10

Binary1 + 1 = 1

Dr. Ihab Talkhan

- Arithmetic operations with numbers in base “ r “ follow the same rules as for decimal numbers

Addition

Subtraction

Dr. Ihab Talkhan

Multiplication

Division

divisor

dividend

subtract

remainder

Dr. Ihab Talkhan

- The rules for subtraction are the same as in decimal, except that a borrow from a given column adds “2” to the minuend digit.
- In division, we have only two choices for the greatest multiple of the divisor Zero and the divisor itself.

Dr. Ihab Talkhan

- Arithmetic operations with Octal , Hexadecimal or any other base “r” system is done by using the following methods:
- Formulation of tables from which one obtains sums and products of two digits in base “r”.
- Converting each pair of digits in a column to decimal , add the digits in decimal, and then convert the result to the corresponding sum and carry in base “r” system.

Dr. Ihab Talkhan

- Add : (59F)16 + (E46)16

Equivalent Decimal

Hexadecimal

Carry 1

=16+5

=16+3

Dr. Ihab Talkhan

- The idea is to add F+6 in hexadecimal, by adding the equivalent decimals 15+6 = 21, then converting (21)10 back to hexadecimal knowing that;
21 = 16+5 gives a sum digit of 5 and a

carry “1” to the next higher

order column digit

Dr. Ihab Talkhan

- The multiplication of two base “r” numbers is done by performing all arithmetic operations in decimal and converting intermediate results one at a time.

Dr. Ihab Talkhan

- Multiply (762)8 x (45)8

carry

Dr. Ihab Talkhan

- Complements are used to simplify the subtraction operation and for logical manipulation.

Given n-digit number N in base r, its r’s complement is;

Given n-digit number N in base r, its r’s complement is;

Dr. Ihab Talkhan

- The r’s complement is obtained by adding “1” to the (r-1)’s complement.
- r’s complement of N can be formed by leaving all least significant 0’s unchanged, then subtracting the first nonzero least significant digit from “r”, and subtracting all higher significant digits from (r-1).
- (r-1)’s complement of N can be formed by subtracting each digit from (r-1).

Dr. Ihab Talkhan

106-246700

- 10’s complement of : 246700 753300
- 9’s complement of : 246700 753299

(106-1)-246700

Dr. Ihab Talkhan

- Note that ; 2n = a binary number which consists of a “1” followed by n 0’s.
- 2n – 1= a binary number represented by n 1’s.
- 2’s complement is formed by leaving all least significant 0’s and the first “1” unchanged, then replacing 1’s with 0’s and 0’s by 1’s in all other higher significant bits.
- 1’s complement is obtained by changing 1’s to 0’s and 0’s to 1’s.

Dr. Ihab Talkhan

- The (r-1)’s complement of Octal or Hexadecimal numbers is obtained by subtracting each digit from 7 or f (15) respectively.
- If the number contains a radix point, then the point should be removed temporarily in order to form the r’s or (r-1)’s complement. The radix point is then restored to the complemented number in the same relative position.
- The complement of the complement restores the number to its original value.

Dr. Ihab Talkhan

- The subtraction method that is based or uses the borrow concept is less efficient than the method that uses complements, when subtraction is implemented with digital hardware.
- The subtraction of two n-digit unsigned numbers, M-N in base “r” is done as follows:
- Add the minuend M to the r’s complement of the subtrahend N;
M + (rn – N) = M- N + rn

- If M≥N, the sum will produce an end carry rn, which is discarded, what is left is the result “ M-N “.
- If M < N, the sum does not produce an end carry and is equal to
rn – (N-M)

which is the r’s complement of (N-M). to obtain the answer in a familiar form, take the r’s complement of the sum and place a negative sign in front.

- Add the minuend M to the r’s complement of the subtrahend N;

Dr. Ihab Talkhan

- Consider the two numbers 72532 & 3250, it is required to apply the rules for subtraction with complements with these two numbers, thus we have two cases:
- Case # 1:
- M = 72532 & N = 3250, required M-N.
- In this case M > N
- Note that M has 5-digits and N has only 4-digits, rule number 1: both numbers must have the same number of digits.
- Note also,, the occurrence of the end carry signifies that M > N and the result is positive.

Dr. Ihab Talkhan

- M – N = 72532 – 03250
7253272532

-03250 +9675010’s Complement

1 69282sum

69282 is therequired answer

Discard the end carry

Dr. Ihab Talkhan

- Case # 2:
- M = 3250 & N = 72532, required M-N.
- In this case M < N
- Note that M has 5-digits and N has only 4-digits, rule number 1: both numbers must have the same number of digits.
- Note also,, the absence of the end carry signifies that M < N and the result is negative.

Dr. Ihab Talkhan

- M – N = 03250 - 72532
0325003250

-72532 +2746810’s Complement

30718sum

The required answer = - ( 10’s complement of 30718)

= - 69282

no carry

Dr. Ihab Talkhan

- When subtracting with complements, the negative answer is recognized by the absence of the end carry and the complemented result.

Dr. Ihab Talkhan

- The (r-1)’s complement can be used when subtracting two unsigned numbers as the (r-1)’s complement is one less than the r’s complement. Thus the result of adding the minuend to the complement of the subtrahend produces a sum which is one less than the correct difference when an end carry occurs.
- Removing the end-carry and adding one to the sum is referred to as an end-around carry.

Dr. Ihab Talkhan

- Example:
X – Y = 1010100 – 1000011

10101001010100

-1000011 +01111001’s Complement

10010000sum

1End-around carry

0010001answer (X-Y)

Dr. Ihab Talkhan

- Example (cont.):
Y – X = 1000011 – 1010100

10000111000011

-1010100 + 01010111’s Complement

1101110sum

Note that, there is no carry in this case

Answer = Y – X = - ( 1’s complement of 1101110)

= - 0010001

Dr. Ihab Talkhan

- Positive integers including zero can be represented as unsigned numbers.
- Because of hardware limitations, computers must represent everything with 1’s & 0’s, including the sign of a number.
- The sign is represented with a bit, placed in the left-most position of the number, where: 0 = positive sign & 1 = negative sign

Dr. Ihab Talkhan

The left most bit represents the sign and the rest of the bits represent the number

The left most bit is the most significant bit of the number

X 1 0 1 0 1 0 1 0 1 1

X = 0 +ve

X = 1 -ve

The left most bit

Dr. Ihab Talkhan

Unsigned 9

Unsigned 25

01001

11001

Signed + 9

Signed - 9

Signed-magnitude System

Dr. Ihab Talkhan

In computers, a signed-complement system is used to represent a negative number, i.e. negative number is represented by its complement.

8-bit representation

+ 9 0 0001001

Signed-magnitude representation 10001001

Signed-1’s complement representation 11110110

Signed-2’s complement representation 11110111

- 9

Dr. Ihab Talkhan

- The addition of two signed numbers, with negative numbers represented in signed 2’s complement form, is obtained from the addition of the two numbers including their sign bits. A carry out of the sign bit position is discarded.
- Note that the negative numbers must be initially in 2’s complement and the sum obtained after the addition, if negative, is in 2’s complement form.

Dr. Ihab Talkhan

+ 60000 0110

+ 130000 1101

+ 19 00010011

+ 60000 0110

- 131111 0011

- 7 1111 1001

- We must ensure that the result has sufficient number of bits to accommodate the sum, if we start with two n-bit numbers and the sum occupies n+1 bits, we say that an overflow occurs.

2’s complement

Dr. Ihab Talkhan

- Note that binary numbers in the signed-complemented system are added and subtracted by the same basic addition and subtraction rules as unsigned numbers, therefore, computers need only one common hardware circuit to handle both types of arithmetic.
- The user / programmer must interpret the results to distinguish between signed and unsigned numbers

Dr. Ihab Talkhan

- The binary code is a group (string) of n bits that assume up to distinct combinations of 1’s and 0’s, with each combination representing one element of the set that is being coded, the bit combination of an n-bit code is determined from the count in binary from 0 to -1.
- Each element must be assigned a unique binary combination and no two elements can have the same value

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Note , a number with “n” decimal digit will require “4n” bits in BCD.
- Note also, a decimal number in BCD is the same as its equivalent binary number, only when the number is between 0 – 9. A BCD number > 10 looks different from its equivalent binary number.
- The binary combinations 1010 – 1111 are not used and have no meaning in the BCD.

Dr. Ihab Talkhan

- It is important to realize that BCD numbers are decimal numbers and not binary numbers.

12 bit

8 bit

Dr. Ihab Talkhan

- Each digit in a BCD does not exceed 9, the sum can not be greater than 9+9+1 = 19, where the “1” being a carry.
- The binary sum will produce a result in the range from 0 to 19, in binary it correspond to 0000 – 10011, but in BCD
0000 – 1 1001, thus when the binary sum is equal to or less 1001 (without a carry) the corresponding BCD is correct.

Dr. Ihab Talkhan

- When the binary sum is , the result is an invalid BCD digit.
- To correct this problem, add binary 6 (0110) to the sum, which converts the sum to a correct BCD digit and produces a carry as required.
- The value 6 corresponds to the 6 invalid combinations in the BCD code (1010 – 1111).

Dr. Ihab Talkhan

40100

+ 50101

9 1001

40100

+ 81000

12 1100

0110

1 0010

81000

+ 91001

17 1 0001

0110

1 0111

Add 6

Sum greater than 9

Sum greater than 16

carry

Dr. Ihab Talkhan

1 1BCD carry

184000110000100

+ 576010101110110

011100001010Binary sum

01100110add 6

760011101100000BCD sum

Dr. Ihab Talkhan

- Multiply 15 x 16 in BCD
15 5 x 6 = 30 L0011 0000

x 16 6 x 1 + 3 = 9 L1001

1001 0000 1 x 5 = 5 L0101

0001 0101 1 x = 1 L0001

0010 1110 0000

0110

0010 0100 0000

1

Dr. Ihab Talkhan

- For signed decimal numbers, the sign is represented with “Four” bits to conform with the 4-bit code of the decimal digits, where:
-ve sign = 1001 (9)

+ve sign = 0000 (0)

- Many computers have special hardware to perform arithmetic calculations directly with decimal numbers in BCD.

Dr. Ihab Talkhan

- Binary codes for decimal digits require a minimum4-bits per digit.
- BCD 8 4 2 1
- Repeated code2 4 2 1
- Excess-3 code
- Negative code 8 4 -2 -1

Weighted codes

Always add 3 (0011) to the original binary number, e.g

0000 0011

0001 0100 and so on

Note, some digits can be coded in two possible ways

Dr. Ihab Talkhan

- The 2421 & Excess-3 codes are self-complementing codes, i.e. the 9’s complement of a decimal number is obtained directly by changing 1’s to 0’s and 0’s to 1’s.
- BCD is not a self-complementing code
- The 84-2-1 accepts positive & negative weights.

Dr. Ihab Talkhan

- You should distinguish between conversion of a decimal number to binary and the binary coding of a decimal number.
- It is important to realize that a string of bits in a computer sometimes represents a binary number and at other times it represents information as specified by a given binary code.

Dr. Ihab Talkhan

- ASCII = American Standard Code for
Information Interchange

- ASCII consists of 7-bits to code 128 characters

26 upper-case letters [ A,B,C,…]

26 lower-case letters [a,b,c,….]

10 decimal numbers [ 0- 9]

32 special printable characters [ #,$,%,&,*,…..]

34 control characters (non-printing C/Cs)

128 characters

Dr. Ihab Talkhan

- Note that, binary codes merely change the symbols not the meaning of the element of information.
- The 34 control characters are used for routing data and arranging the printed text into the prescribed format

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- ASCII code was modified to 8-bits instead of 7-bits. (ASCII is 1 byte in length)
- 1 byte = 8 bits
- The extra bit, whose position is in the most significant bit [ default is “0”] , is used for:
- Providing additional symbols such as the Greek Alphabet or italic type format……etc
- Indicating the parity of the character when used for data communication.

Dr. Ihab Talkhan

- The parity bit is an extra bit included to make the total number of 1’s in a row either even or odd.
- The bit is helpful in detecting errors during the transmission of information from one location to another.

Even parity

Dr. Ihab Talkhan

- EBCDIC = Extended BCD Interchange Code, used in IBM. It is 8-bits for each character and a 9th bit for parity.

Dr. Ihab Talkhan

- Digital circuits are hardware components that manipulate binary information.
- Gates are circuits that are constructed with electronics components [ transistors, diodes, and resistors]
- Boolean algebra is a binary logic system which is a mathematical notation that specifies the operation of a gate [ Boolean => the English mathematician “George Boole” 1854 ]

Dr. Ihab Talkhan

Voltage

5

Logic – 1 range

2

Intermediate region, crossed only during state transition

Transition , occurs between the two limits

0.8

Logic – 0 range

0

time

- Electrical Signals [ voltages or currents ] that exist throughout a digital system is in either of two recognizable values [ logic-1 or logic 0 ]

Dr. Ihab Talkhan

- You should distinguish between binary logic and binary arithmetic. Arithmetic variables are numbers that consist of many digits. A logic variable is always either 1 or 0.
- A Truth Table is a table of combinations of the binary variables showing the relationship between the values that the variables take and the result of the operation.
- The number of rows in the Truth Table is , n = number of variables in the function.
- The binary combinations are obtained from the binary number by counting from 0 to

Dr. Ihab Talkhan

Carry

Two digits

Arithmetic 1 + 1 = 10

Binary1 + 1 = 1

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- AND and OR gates may have more than two inputs.
- Timing diagrams illustrate the response of any gate to all possible input signal combinations.
- The horizontal axis of the timing diagram represents time and th vertical axis represents the signal as it changes between the two possible voltage levels

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Language description
- Function description
- Boolean Equation
- Graphic Symbols
- Truth Table
- Timing Diagram
- Coding (HDL)

Dr. Ihab Talkhan

Z = X . Y

Z = X + Y

Dr. Ihab Talkhan

Using NOR Gates

Using NAND Gates

Basic Function

A

A

A

A

NOT (inverter)

A

A

AND

AB

AB

B

B

A

A

A+B

OR

A+B

B

B

Dr. Ihab Talkhan

- It is an algebra that deals with binary variables and logic operations:
- A Boolean function consists of:
- An algebraic expression formed with binary variables.
- The constants “0” and “1”
- The logic operation symbol ( . , +, NOT)
- Parentheses and an equal sign

Dr. Ihab Talkhan

- Given a logic function “F”, defined as follows:
- F = 1 if X = 1 or if both Y & Z are equal to 1
0 otherwise

- The logic equation that represents the above function is given by:

- F = 1 if X = 1 or if both Y & Z are equal to 1

Dr. Ihab Talkhan

- The truth table for the given function is as shown.
- The Boolean function can be transformed from an algebraic expression into a circuit diagram composed of logic gates.

Dr. Ihab Talkhan

X

Y

Z

OR

AND

output

Complement = need an inverter

Note : the number of inputs equal the number of variables

Dr. Ihab Talkhan

- There is only one way to represent a Boolean function in a Truth Table, where there are a variety of ways to represent the function when it is in algebraic form.
- By manipulating a Boolean expression according to Boolean Algebra rules, it is sometimes possible to obtain a simpler expression for the same function, thus reducing the number of gates in the circuit.

Dr. Ihab Talkhan

Duality

Dr. Ihab Talkhan

- The dual of an algebraic expression is obtained by interchanging OR and AND operations and replacing 1’s by 0’s and 0’s by 1’s.
- Notice that when evaluating an expression, the complement over a single variable is evaluated first , then the AND operation and the OR operation
( ) NOT AND OR

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Which Shows that the term YZ is redundant and can be eliminated
- Proof:

Dr. Ihab Talkhan

- Notice that, two terms are associated with one variable and its complement and the redundant term is the one which not contain the same variable.

Dr. Ihab Talkhan

- The complement of a function “F” is obtained by interchanging 1’s to 0’s and 0’s to 1’s in the values of “F” in the Truth Table.
- OR, it can be derived algebraically by applying DeMorgan’s Theorem.
- The complement of an expression is obtained by interchanging AND and OR operations and complementing each variable.

Dr. Ihab Talkhan

- Or by taking the dual of the expression:
- The original function
- The dual of F
- Complement each literal

- The complement of a function is done by taking the dual of the function and complement each literal.

Dr. Ihab Talkhan

AND operation among several variables

0 = complemented variable

1 = uncomplemented variable

OR operation among several variables

1 = complemented variable

0 = uncomplemented variable

- A product term in which all the variables appear exactly once either complemented or uncomplemented is called a “minterm”, note that there are distinct “minterm” for n-variables.

Dr. Ihab Talkhan

- An algebraic expression representing the function is derived from the Truth Table by finding the logical sun of all product terms for which the function assumes the binary value of “1”.
- A symbol for each minterm , where “j” denotes the decimal equivalent of the binary number of the minterm.
- A sum term that contain all the variables in complemented or uncomplemented form is called “maxterm”, symbol
- Note that

Dr. Ihab Talkhan

Example

Dr. Ihab Talkhan

- Sum of Product SOP
- Product of Sum POS
- Note that the decimal numbers included in the product of maxterms will always be the same as the minterm list of the complement function

Dr. Ihab Talkhan

- There are minterm for n-Boolean variables which can be evaluated from the binary numbers 0 to
- Any Boolean function can be expressed as a logical sum of minterms.
- The complement of a function contains those minterms not included in the original function
- A function that includes all minterms is equal to logic-1.

Dr. Ihab Talkhan

- AND gates followed by OR gate forms a circuit configuration that is referred to as a Two-Level implementation (SOP).
- Two-Level implementation is preferred as it produces the least amount of delay time through the system.
- Delay is defined as the time that a signal spends to propagate from input to output.
- Also, Product of Sum (POS) is a two-level implementation, as it consists of a group of OR gates followed by an AND gate.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Each square corresponds to a row of the Truth-Table and to one minterm of the algebraic equation.
- Only one digit changing value between two adjacent rows and columns.
- One square represent one minterm, giving a term of four variables (in case of 4-varaiable map).
- Two adjacent squares represent a term of three literals
- Four adjacent squares represent a term of two literals.
- Eight adjacent squares represent a term of one literal.
- Sixteen adjacent squares represent F=1.
- When a variable appears within a group in both inverted and non-inverted state, then the variable can be eliminated.

Dr. Ihab Talkhan

- Fill the map from the Truth-Table.
- Look at 1’s (where F=1).
- Make the biggest group possible:
- Any square can appear in more than one group.
- Get expression for each group.
- OR all expressions.

- Squares in a group = , n=0,1,2,…
- Adjacent cells
- Cover all 1’s

Dr. Ihab Talkhan

One digit change value at a time

CD

AB

Cell

POS

SOP

Dr. Ihab Talkhan

- Note that there are cases where two squares in the map are considered to be adjacent,, even though they do not touch each other.

YZ

X

Dr. Ihab Talkhan

1

1

1

1

1

1

1

1

1

1

1

CD

AB

Dr. Ihab Talkhan

CD

AB

1

1

1

1

1

1

1

Dr. Ihab Talkhan

- A prime implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map.
- If a minterm in a square is covered by only one prime implicant , that prime implicant is said to be essential.

Dr. Ihab Talkhan

YZ

X

1

1

1

1

1

Dr. Ihab Talkhan

1

1

1

1

1

1

1

1

CD

AB

Non-essential prime implicant

essential prime implicants

Dr. Ihab Talkhan

- Note that, once the essential prime implicants are taken, the third term is not needed (redundant), as all the minterms are already covered by the essential prime implicants, thus:

Dr. Ihab Talkhan

CD

AB

1

1

1

1

1

1

1

Non-essential

or

Dr. Ihab Talkhan

- The complement of a function is represented in the K-map by the squares (cells) not marked by 1’s.

Dr. Ihab Talkhan

- To represent any function as a product of sums (POS), we take the dual of and complementing each literal, i.e. we get:

Dr. Ihab Talkhan

CD

AB

1

1

1

1

1

1

1

Dr. Ihab Talkhan

- There are applications where the function is not specified for certain combinations of variables, e.g. the four-bit binary code (BCD code) where there are six combinations from 10 – 15 which are not used and consequently are considered as unspecified.
- These unspecified minterms are called “don’t care” terms and can be used on a map to provide further simplification of the function by considering it as 1’s or 0’s (depending on the situation).
- Don’t care terms are represented by a cross “X” in the map.

Dr. Ihab Talkhan

CD

AB

X

1

1

X

X

1

1

1

Algebraically these two functions are not equal , as both covers different don’t care minterms, but the original function is satisfied as don’t care terms will not affect the original function

Dr. Ihab Talkhan

- Five-variable map needs 32-cell
- Six-variable map needs 64-cell & so on.
- In general, maps with six or more variables needs too many cells and they are impractical to be analyzed manually, there special program (simulation programs) that can handle such situation.

Dr. Ihab Talkhan

- We use two four-variables maps, the first one has a the variable A=0 as a common factor, and the second has a common factor A=1.
- Each cell in the A=0 map is adjacent to the corresponding cell in the A=1 map, e.g.
- Any adjacent cells , k=0,1,2,3,4, in the 5-variable map represents a product term of 5-k literals.

Dr. Ihab Talkhan

DE

DE

BC

BC

A=0

A=1

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DE

DE

BC

BC

1

1

1

1

1

1

1

1

1

1

1

common

A=1

A=0

Dr. Ihab Talkhan

Dr. Ihab Talkhan

X

X

Y

Y

Invert-OR

AND-invert

- NAND and NOR gates are more popular than AND and OR gates, as they are easily constructed with electronic circuits and Boolean functions can be easily implemented with them.

Two Graphic Symbols for a NAND gate

Dr. Ihab Talkhan

X

X

Y

Y

OR-invert

invert-AND

Two Graphic Symbols for a NOR gate

Dr. Ihab Talkhan

Mixed notation, both AND-invert & invert-OR are present

- The implementation of Boolean functions with NAND gates requires that the function be in the SOP form.

Doubleinversion

AND & OR gates

NAND gates

Dr. Ihab Talkhan

1

1

1

1

1

1

Note that Z must have a one-input NAND gate to compensate for the small circle in the second level gate

Dr. Ihab Talkhan

- Simplify the function (SOP)
- Draw a NAND gate for each product term and the inputs to each NAND gate are the literals of the product term. (group of the first-level gates)
- Draw a single gate using AND-invert or invert-OR graphic symbol in the second level.
- A term with a single literal requires an inverter in the first level.

Dr. Ihab Talkhan

- Convert all AND/OR using AND-invert/invert-OR.
- Check all the small circles in the diagram. For every small circle that is not counteracted by anther small circle along the same line, insert an inverter (one-input NAND gate) or complement the input variable.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

XNOR is equal to “1” if both X & Y are equal to “1” or both are equal to “0”

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- It used for error detection.
- The circuit that generates the parity bit in the transmitter is called a parity generator.
- The circuit that checks the parity in the receiver is called a parity checker.

Dr. Ihab Talkhan

Parity Checker

Parity generator

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TG

- This gate is available with CMOS type electronic circuits.

X & Y are inputs

C & are control inputs

Open Switch

Pass signal

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TG1

TG2

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- It is a small silicon semiconductor crystal, called a chip, containing the electronic components for the digital gates.
- Number of pins may range from 14 in a small OC package to 64 or more in a large package.

Dr. Ihab Talkhan

- 100 – few thousands gates
- Processors
- Memory chips
- Programmable modules

- No. of gates < 10
- Inputs & outputs are connected directly to the pins

- 10 -100 gates
- Decoder
- Adders
- Registers

Dr. Ihab Talkhan

- Basic circuits in each technology is a NAND, NOR or an inverter.

- High component density
- Simple processing technique during fabrication

- High speed operation
- Super computers
- Signal processors

- Diodes/transistors
- Power supply 5 V
- Two logic levels [0V - 3.5V]
- Standard

- Low power consumption

Dr. Ihab Talkhan

- There are many type of the TTL family
- High-speed TTL
- Low-power TTL
- Schottky TTL
- Low-power Schottky TTL
- Advanced Low-power Shcottky TTL

- ECL gates operates in a nano-saturated state, a condition that allows the achievement of propagation delays of 1-2 nanoseconds.

Dr. Ihab Talkhan

- Fan-out
- Power-dissipation
- Propagation delay
- Noise margin

Dr. Ihab Talkhan

- It specifies the number of standard loads that the output of a typical gate can drive without impairing its normal operation.
- A standard load is usually defined as the amount of current needed by an input of another similar gate of the same family.

Dr. Ihab Talkhan

- It is the power consumed by the gate which must be available from the power supply.

Dr. Ihab Talkhan

- It is the average transition delay time for the signal to propagate from input to output when the binary changes in value. The operating speed is inversely proportional to the propagation delay.

Dr. Ihab Talkhan

- It is the maximum external noise voltage that causes an undesirable change in the circuit output.

Dr. Ihab Talkhan

- Choosing the high-level “H” to represent logic “1” defines a positive logic system.
- Choosing the low-level “L” to represent logic “1” defines a negative logic system.

Signal value

Logic value

Logic value

Signal value

Negative logic

Positive logic

Dr. Ihab Talkhan

- The signal values “H” & “L” are usually used in the components data sheets
- The actual truth table is defined according to the definition of “H” and “L” in the data sheet.

Dr. Ihab Talkhan

X

TTL Gate

Z

Data Sheet

Y

Depending on the definition of H & L in the data sheet

X

X

Z

Z

Y

Y

These small triangle in the inputs & output designate a polarity indicator

Dr. Ihab Talkhan

Consists of logic gates whose outputs at any time are determined directly from the values of the present inputs.

No feedback or storage elements are involved.

It involves storage elements (Flip-Flops).

Outputs are a function of inputs and the state of the storage elements, where the state of the storage elements is a function of the previous inputs.

Circuit behavior must be specified by a time sequence of inputs and internal states.

Dr. Ihab Talkhan

Logic Circuits

Dr. Ihab Talkhan

- A sequential circuit is specified by a time sequence of inputs, outputs and internal states. It contain memory and thus can remember the changes of input signals that occurred in the past.
- Inputs for the sequential circuit are functions of external inputs and the present state of the storage elements.
- Both external inputs and the present states determine the binary value of the outputs and the condition for changing the state of the storage state.

Outputs = f( external inputs , present states)

Next state = f( external inputs , present states)

Dr. Ihab Talkhan

- To obtain the output Boolean functions from a logic diagram:
- Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the Boolean functions for each gate.
- Label the gates that are a function of input variables and previous labeled gates with different arbitrary symbols. Find the Boolean functions for these gates.
- Repeat step 2 until the outputs of the circuit are obtained in terms of the input variables.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Thus the Boolean functions of F1 and F2 are:

Dr. Ihab Talkhan

- Determine the number of input variables in the circuit for n-inputs, list the binary number from 0 to 2n-1 in a table.
- Label the outputs of the selected gates with arbitrary symbols.
- Obtain the Truth Table for the outputs of those gates that are a function of the input variables only.
- Proceed to obtain the Truth Table for the outputs of those gates that are a function of previously defined values until the columns for all outputs are determined.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Form the specifications of the circuit, determine the required number of inputs and outputs and assign a letter (symbol) to each.
- Derive the Truth Table that defines the required relationship between inputs and outputs.
- Obtain the simplified Boolean functions for each output as a function of the input variables.
- Draw the logic diagram.

Dr. Ihab Talkhan

- Minimum number of gates
- Minimum number of inputs to a gate
- Minimum propagation delay of the signal through the gates
- Minimum number of interconnections

Dr. Ihab Talkhan

- Design a combinational circuit with three inputs and one output. The output must equal “1” when the inputs are less than three and “0” otherwise. [use only NAND gates]

Dr. Ihab Talkhan

1

1

1

YZ

X

Mixed-symbol notation

Dr. Ihab Talkhan

- When a combinational circuit has two or more outputs, each output must be expressed separately as a function of all the input variables.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

CD

CD

AB

AB

Dr. Ihab Talkhan

CD

CD

AB

AB

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Digital read-out found in electronic caculators and digital watches use display devices such as light emitting diodes LED or liquid crystal display LCD, each digit of the display is formed from seven segments.
- Each consists of one LED or one crystal which can be illuminated by digital signals.

Dr. Ihab Talkhan

a

f

b

g

e

c

d

7-outputs

Dr. Ihab Talkhan

- We cannot use the don’t care condition here for the six binary combinations 10101 – 1111, as the design will most likely produce some arbitrary and meaningless display of the unused combinations.

14 AND gate and 7 OR

Dr. Ihab Talkhan

- An arithmetic circuit is a combinational circuit that performs arithmetic operations such as addition, subtraction, multiplication and division with binary numbers or with decimal numbers in a binary code.
0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 10

- A combinational circuit that performs the addition of two bits is called a “Half Adder”.

One digit

Carry is added to the next higher order pair of significant bits

Two digits

Dr. Ihab Talkhan

- A combinational circuit that performs the addition of three bits (two significant bits and a previous carry) is called a “Full Adder”.
- Two Half Adders are employed to implement a Full Adder.
- The Full adder circuit is the basic arithmetic component from which all other arithmetic circuits are constructed.

Dr. Ihab Talkhan

- It is an arithmetic circuit that generates the sum of two binary digits.

Half-Adder

Dr. Ihab Talkhan

- It is a combinational circuit that forms the arithmetic sum of three input bits.

Carry from the previous lower significant position

Dr. Ihab Talkhan

YZ

X

YZ

X

Dr. Ihab Talkhan

FA

FA

FA

FA

4-bit Parallel Adder

- The sum of two n-bit binary numbers can be generated in serial or parallel fashion.
- The serial addition method uses only one Full Adder and a Storage device to hold the output carry.
- The parallel method uses n-Full Adders and all bits are applied simultaneously to produce the sum.

Dr. Ihab Talkhan

A = 1011B = 0011

Dr. Ihab Talkhan

- The subtraction of binary number can be done most conveniently by means of complements
- The subtraction “ A-B “ is done by taking the 2’s complement of “ B “ and adding it to “ A “.
- The 2’s complement can be obtained by taking the 1’s complement and adding “1” to the least significant bit.
- The 1’s complement can be implemented easily with inverter circuit and we can add “1” to the sum by making the initial input carry of the parallel adder equal to “1”.

Dr. Ihab Talkhan

S = C0 = 0 addition

S = C0 = 1 Subtraction

FA

FA

FA

FA

Adder/Subtractor Circuit

Dr. Ihab Talkhan

- An adder that perform arithmetic operations directly with decimal number system employ arithmetic circuit that accept decimal numbers and present results in the same code.
- It requires a minimum of nine inputs and five outputs, Four bits to code each decimal digit and the circuit must have an input and output carry.
- When C=0 , nothing is added to the binary sum
- When C=1, binary 0110 is added to the binary sum through the second 4-bit adder.
- Any output carry from the second binary adder can be neglected.
- A decimal parallel adder that adds two n-decimal digits needs n BCD adders, the output carry from each BCD adder must be connected to the input carry of the adder in the next higher position.

Dr. Ihab Talkhan

Addend

Augend

4-bit binary adder

4-bit binary adder

input

carry

Condition for correction:

Detect the binary output from 1010 - 1111

Output carry from the first Adder

BCD sum

Output carry

Dr. Ihab Talkhan

- The multiplicand is multiplied by each bit of the multiplier, starting from the least significant bit.
- Such multiplication forms a partial products.
- Successive partial products are shifted one position to the left.
- The final product is obtained from the sum of the partial products.
- For “j” multiplier bits and “k” multiplicand bits , we need jxk AND gates and (j-1)k bit adders to produce a product of j+k bits.

Dr. Ihab Talkhan

HA

HA

2-bit by 2-bit binary multiplier

Dr. Ihab Talkhan

- Discrete quantities of information are represented in digital computers with binary codes.
- A binary code of n-bits is capable of representing up to 2n distinct elements of coded information.
- A decoder is a combinational circuit that converts binary information from n-coded inputs to a maximum of 2n unique outputs.
- A decoder has n inputs and m outputs and is referred to as “ nxm decoder”

Dr. Ihab Talkhan

Dr. Ihab Talkhan

A0

D0

A1

D1

D2

D3

E

Dr. Ihab Talkhan

- Implement a Full Adder circuit with a decoder and OR gates:
- Three inputs a total of eight minterms we need a 3-to-8 line decoder.
- This Decoder generates the eight minterms of X,Y,Z.
- The OR gate for output S forms the logical sum of minterm 1,2,4,aand 7.
- The OR gate of output C forms the logical sum of minterms 3,5,6 and 7.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

S

Z

20

Y

21

X

22

C

3x8 Decoder

Dr. Ihab Talkhan

- An Encoder has 2n (or less) input lines and n output lines.

Dr. Ihab Talkhan

- It is a combinatinal circuit that implements the priority function.
- The operation of the priority Encoder is such that, if two or more inputs are equal to “1” at the same time, the input having the highest priority will take precedence.
- The input D3 in the following Truth Table has the highest priority, regardless of the values of the other inputs.
- Thus, if D3 is “1” , the output will indicate that A1A0 = 11, i.e. the code A1A0 = 11 means that any data appears on line D3 will have the highest priority and pass through the system irrespective of the other inputs.
- If D2 = “1” and D3 = “0” the code A1A0 = 10 and this means that D2 has the highest priority in this case.

Dr. Ihab Talkhan

D1D0

D1D0

D3D2

D3D2

Dr. Ihab Talkhan

D3

A0

D2

A1

D1

V

D0

4-input Priority Encoder

Dr. Ihab Talkhan

- It is a combinational circuit that selects binary information from one of many lines and directs it to a single output line.
- The selection of a particular input line is controlled by a set of selection variables.
- Normally, there are 2n input lines and “n” selection variables whose bit combinations determine which input is selected.
- As in decoders, multiplexers may have an enable input to control the operation of the unit.
- When the enable input is in the active state, the outputs are disabled.
- The enable input is useful for expanding two or more multiplexers onto a multiplexer with a larger number of inputs.

Dr. Ihab Talkhan

S0

S1

D0

D1

Y

D2

D3

4-to-1 line Multiplexer ( MUX )

[ Data Selector ]

Dr. Ihab Talkhan

- The first “n-1” variables of the function are connected to the selection inputs of the multiplexer.
- The remaining single variable of the function is used for the data inputs.
- If the single variable is “Z”, the data input of the multiplexer will be either ;

Dr. Ihab Talkhan

4 x 1 MUX

Dr. Ihab Talkhan

- The Boolean function is first listed in a truth table.
- The first “n-1” variables listed in the table are applied to the selection inputs of the MUX.
- For each combination of the selection variables, we evaluate the output as a function of the last variable.
- This can be 0, 1, the variable or the complement of the variable.

Dr. Ihab Talkhan

- It is a digital function that performs the inverse operation of a MUX.
- It receives information from a single line and transmits it to one of 2n possible output lines.
- The selection of the specific output is controlled by the bit combination of n-selection lines.

Dr. Ihab Talkhan

E

S0

D0

D1

S1

D2

D3

1-to-4 Demultiplexer

Dr. Ihab Talkhan

Sequential Circuits

Consists of logic gates whose outputs at any time are determined directly from the values of the present inputs.

No feedback or storage elements are involved.

It involves storage elements (Flip-Flops).

Outputs are a function of inputs and the state of the storage elements, where the state of the storage elements is a function of the previous inputs.

Circuit behavior must be specified by a time sequence of inputs and internal states.

Dr. Ihab Talkhan

Logic Circuits

Dr. Ihab Talkhan

- A sequential circuit is specified by a time sequence of inputs, outputs and internal states. It contain memory and thus can remember the changes of input signals that occurred in the past.
- Inputs for the sequential circuit are functions of external inputs and the present state of the storage elements.
- Both external inputs and the present states determine the binary value of the outputs and the condition for changing the state of the storage state.

Outputs = f( external inputs , present states)

Next state = f( external inputs , present states)

Dr. Ihab Talkhan

Sequential Circuits

- It is a system whose behavior depends upon the order in which the inputs change, and the state of the circuit can be affected at any instant of time

- It is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time

Dr. Ihab Talkhan

- An asynchronous sequential circuit may be regarded as a combinational circuit with feedback, thus the system may operate in an unpredictable manner and sometimes may even become unstable.
- The various problems encountered in asynchronous systems impose many difficulties on the designer, and for this reason they are seldom used.
- A synchronous sequential circuit employs signals that affect the storage elements only at discrete instant of time, as synchronization is achieved by a timing device called a “Clock Generator” that produces a periodic train of clock pulses.

Dr. Ihab Talkhan

- The clock pulses are distributed throughout the system in such a way that storage elements are affected only upon the arrival of each pulse, the outputs of the storage elements change only when clock pulses are present.
- The storage elements employed in clocked sequential circuits are called “Flip-Flops”.
- A Flip-Flop is a binary storage device capable of storing one bit of information.
- When a clock pulse is not active, the feedback loop is broken because the Flip-Flop outputs cannot change even if the outputs of the combinational circuit change in value, thus the transition from one state to the other occurs only at predetermined time intervals dictated by the clock pulses.

Dr. Ihab Talkhan

Outputs

inputs

Combinational Circuit

Next state change only during a clock pulse transition

Next

state

FLIP-Flop

Clock pulses

Present state

Synchronous clocked sequential circuit

Dr. Ihab Talkhan

- A Flip-Flop circuit has two outputs, one for the normal value and the other for the complemented value of the bit that is stored in it.

Dr. Ihab Talkhan

- A Flip-Flop circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states.
- Latches are the basic circuit from which all Flip-Flops are constructed.

Dr. Ihab Talkhan

Action that must be taken

reset

set

No change

SR-Latch with NOR gates

Dr. Ihab Talkhan

SR-Latch (NAND gates)

Action that must be taken

set

reset

No change

SR-Latch with NAND gates

Dr. Ihab Talkhan

- Notice that, the S input in the SR NOR-Latch must go back to “0” before any other changes can occur.
- There are two input conditions that cause the circuit to be in the SET state, the first is the action that must be taken by input S to bring the circuit to the SET state, the second is the removing of the active input from S leaving the circuit in the same state.
- When S=R=1 (NOR-gate latch), both outputs go to “0”, this produces an undefined state and it also violates the requirement that output Q and Q be the complement of each other.

Dr. Ihab Talkhan

- Comparing the SR NAND-Latch and the SR NOR-Latch, we note that the input signals for the NAND required the complement values of those used for the NOR-Latch.
- Because the NAND-Latch require a “0” signal to change its state, it is sometimes referred to as an S-R Latch, the bar above the letters designates the fact that the inputs must be in their complement form to activate the circuit.

Dr. Ihab Talkhan

SR-Latch (NAND gates)

set

reset

SR-Latch with NAND gates

and a control input

Dr. Ihab Talkhan

- An additional control input which determines when the state of the latch can be changed is added to the basic SR-Latch to improve its operation
- The control input C acts as an enable signal for the other two inputs.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- One way to eliminate the undesirable condition of the indeterminate state in the SR-Latch is to insure that inputs S & R are never equal to 1 at the same time.
- As long as the control input is at “0”, the cross-coupled SR latch has both inputs at the 1 level and the circuit can not change regardless of the value of D.

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Obtain the binary values of each Flip-Flop input equation in terms of the present state and input variables
- Use the corresponding Flip-Flop characteristic table to determine the next state.

Dr. Ihab Talkhan

- The characteristic tables are a shorter version of the truth table, it gives for every set of input values and the state of the Flip-Flop before the rising-end (edge) the corresponding state of the Flip-Flop after the rising edge of the clock signal.
- By using K-map we can derive the characteristic equation for each Flip-Flop

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- The excitation for each Flip-Flop, is used during the analysis of sequential circuits. It is derived from the characteristic table by transposing input and output columns.
- It gives the value of the Flip-Flop‘s inputs that are necessary to change the Flip-Flop’s present state to the desired next state after the rising edge of the clock signal.

Dr. Ihab Talkhan

- In addition to graphical symbols, tables, or equations, Flip-Flops can also be described uniquely by means of State diagrams or State graphs, in which case each state would be represented by a circle , and a transition between state would be represented by an arrow.

Dr. Ihab Talkhan

SR = 10

SR =00 or 01

SR =00 or 10

Q=1

Q=1

Q=0

Q=0

SR = 01

SR Flip-Flop

JK = 10 or 11

JK =00 or 01

JK =00 or 10

JK = 01or 11

JK Flip-Flop

Dr. Ihab Talkhan

D = 1

D = 0

D = 1

Q=1

Q=1

Q=0

Q=0

D = 0

D Flip-Flop

T = 1

T = 0

T = 0

T = 1

T Flip-Flop

State Diagram for various Flip-Flops

Dr. Ihab Talkhan

- The state diagram can be obtained directly from the state table.
- The state is represented by a circle and the transition between state is indicated by a directed lines connecting the circles.
- The directed lines are labeled with two binary numbers separated by a slash, the input value during present state and the second is the output during the present state.
- Same state can represent both the source and destination of a transition.
- Each state can be thought of as a time interval between two rising edges of the clock signal.

Dr. Ihab Talkhan

Q=1

Q=0

During present state

Input / output

State of a Flip-Flop

Directed line

Dr. Ihab Talkhan

- Consider a sequential circuit with two JK Flip-Flops (A & B) and one input “X”, specified by the following input equations:

Dr. Ihab Talkhan

B

A

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- Find , , , from the equations
- Find the next state from the corresponding J & K inputs using the characteristic table of the JK Flip-Flop.

Dr. Ihab Talkhan

Value of input X

0

1

01

00

0

0

0

1

1

11

10

0

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- It consists of two Latches and an inverter.
- When clock pulse input C=“1”, then the output of the inverter is “0”. Thus the Master is enabled and its output Y is equal to the external input D and the Slave is disabled.
- When clock pulse input C=“0”, then the output of the inverter is “1”. Thus the Slave is enabled and its output Q is equal to the Master output Y and the Master is disabled.
- Any changes in the external D input changes the master output Y but cannot affect the Slave output Q.

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SLAVE

MASTER

External D

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- Replacing the Master D Latch with an SR Latch with control input, the result is a Master-Slave SR Flip-Flop. But the SP Flip-Flop has the undesirable condition of producing an indeterminate next state when S=R=1.
- A modified version of the SR Flip-Flop that eliminates the undesirable condition is the JK Flip-Flop, in this case when J=K=1, it causes the output to complement its value

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MASTER

SLAVE

S

R

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- Each Flip-Flop is usually available with and without asynchronous inputs, that are used to preset and clear the Flip-Flops independently of other Flip-Flop inputs.
- These inputs are used to set the Flip-Flops into initial state for their standard operation, as when power is turned on, the state of each Flip-Flop is not predictable, thus we must use asynchronous inputs to set the Flip-Flop properly.
- Asynchronous means, inputs do not depend on the clock signal and therefore have precedence over all other operations.

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C

CLR & PRS are asynchronous inputs

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Active-high CLR & PRS

Active-low CLR & PRS

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- It is divided into three Latches:
- The SET latch
- The Reset Latch
- The Output Latch

- A low value of asynchronous signals affects the FLIP-Flop:
- The Latch is preset by the signal PRS = 0
- The Latch is cleared by the signal CLR = 0

- Note that, the preset and clear signals force all the latches into proper states that correspond to Q = 1 & Q = 0 respectively.

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SET Latch

OUTPUT Latch

RESET Latch

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- Active-low preset and clear signals are more frequently found in practice.
- Note that, the SET latch follows the changes in the CLK signal if D is equal to “1” at the rising edge of the CLK signal, while the RESET latch follows the CLK signal if D=0 at the rising edge of the CLK signal.

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- The simplest of the storage components.
- Each register consists of n-Flip-Flops driven by a common clock signal.
- SET (Preset) and RESET (Clear) inputs are independent of the clock signal and have priority over it.
- The register store any new data automatically on every rising edge of the clock.

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Preset

I3 I2 I1 I0

CLK

Q3 Q2 Q1 Q0

Clear

4-bit register

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- To control the input data of a register, a selector (Multiplexer [MUX]) unit is used, where a selector is a device that accepts many inputs and selects only one of them at a time to represent the output [ 2n-inputs, n-control and one output ].
- A control signal “LOAD” or “Enable” is used, which allows loading the data into the register [parallel-load register].
- The selector, selects either input data or data already stored in the register.

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Load = 1 enter new data (Ii , i = 0,1,2,3)

0 enter previous stored data (Qi , i = 0,1,2,3)

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- It shifts its contents one bit in the specified direction when the control signal “SHIFT” is equal to “1”.
- It is used to convert a serial data stream into a parallel stream.

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4-bit serial-in/parallel-out

Shift-right register

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- By using a 4-to-1 Selector, you can combine the SHIFT and LOADING functions into one unit.
- It either shift its contents or load new data.
- It could shift one-bit either to the left or to the right depending on the selection mode.

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Dr. Ihab Talkhan

3

3

3

3

2

2

2

2

1

1

1

1

0

0

0

0

Dr. Ihab Talkhan

- A counter is a special type of a register.
- It incorporates an incremental, which allows it to count upward or downward.
- The incremental consists of a series of Half-Adders [HA] arranged such that an HA in bit position “i” will have two inputs connected to the output of the Flip-Flop Qi and the carry Ci from he HA in position “i-1”.
- The counter equation is as follows:
- As long as E=1, the counter will count-up modulo 4, adding “1” to its content on every rising edge of the clock.

Dr. Ihab Talkhan

Enable

E

>

Counter

Q2 Q1 Q0

Clear

Three states 3 Flip-Flops, we will use D F.F. as an example

Enable = 0 no change

= 1 count

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Q1Q0

Q1Q0

Q2

Q2

Q1Q0

Q2

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E

C0

C1

C2

C3

carry

D2

D1

D0

Q2

Q1

Q0

Half-Adder

3-bit up-counter

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Dr. Ihab Talkhan

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Dr. Ihab Talkhan

- The previous counter can be extended to represent an up/down counter, if we replace the Half-Adder with a Half-Adder/Subtractor [HAS], which can increment or decrement under the control of a direction signal “ D “, in this case the counter equation will be:

Dr. Ihab Talkhan

Direction signal , D = 0 count up, D = 1 count down

D

E

C0

C3

C1

C2

Carry

D1

D0

D2

CLEAR

CLK

Q2

Q0

Q1

4-bit up/down Binary Counter

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D

E = Ci

Ci+1

Di

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I2

I1

I0

D

E

Output carry

HAS

HAS

HAS

Selector

Selector

Selector

Load

Clear

CLK

Q2

Q0

Q1

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- It can be constructed by detecting when the counter reaches a count of “9” and loading “0” instead of “10” in the next clock cycle.
- The detection is accomplished by an AND gate whose output is equal to “1” when the content of the counter is equal to “1001”.
- The output of the AND is connected to the Counter's Load input, which allows the counter to load “0” at the next rising edge of the clock.
- In the up direction we must load “0” into the counter when it reaches a count of “9”, while in the down direction we must load “9” when the counter reaches a count of “0”.

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0

0

0

0

0

Up/Down Counter

BCD up-counter

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Up/Down BCD Counter

Selector

S

Up/Down Counter

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- All Flip-Flops are not all clocked by the same clock signal
- There is no need to use an incremental or decremental, counting is achieved by toggling each Flip-Flop at half the frequency of the preceding Flip-Flop.
- The Flip-Flop will change its state on every 0-to-1 transition of its clock input.
- Note, the clock signal “CLK” is used to only clock the Flip-Flop in the least significant position.
- The clock-to-output delay of the ith Flip-Flop is equal to “i”.
- The maximum counting frequency of an n-bit asynchronous counter is:

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T

T

T

T

4-bit Asynchronous Up-Counter

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t0

t1

t2

t3

t4

t5

t6

t7

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- To speed up an asynchronous counter, we must make it partly synchronous.
- To do this, we divide a large counter into n-bit slices, so that the operation within each slice is asynchronous, while the propagation between slices is synchronous, or vice versa.

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Asynchronous

Counter

Asynchronous

Counter

Synchronous Counter with 4-bit Asynchronous Slices

8-bit Mixed-mode Counter

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Synchronous

Counter

Synchronous

Counter

Asynchronous Counter with 4-bit Synchronous Slices

8-bit Mixed-mode Counter

Dr. Ihab Talkhan

Memory & Programmable Logic

- For any system, there are three major units:
- Central processing unit CPU
- Memory unit
- Input/Output unit

- In digital system, memory is a collection of cells capable of storing binary information (permanent or temporary).
- It contains electronic circuits for storing and retrieving information.
- It interacts with the CPU and input/output units.

Dr. Ihab Talkhan

- It is a programmable logic devices PLDs, which are integrated circuits with internal logic gates connected through electronic fuses.
- Programming is done by blowing these fuses to obtain the desired logic function.

- Accept new information for storage to be available later for use (write)
- Transfer stored information out of memory (read)
- RAMs may range on size from hundreds to billions of bits.
- It is volatile

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Conventional Symbol

Array Logic Symbol

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Dr. Ihab Talkhan

- To establish the programmable connections the following technologies are used:
- EPROM
- EEPROM
- FLASH

Dr. Ihab Talkhan

- used to create a wired –AND function. The transistor has two gates, a select gate and a floating gate, charge can be accumulated and trapped on the floating gate by a mechanism called avalanche injection or hot electron injection. These transistors are referred to as FAMOS (Floating gate Avalanche-injection MOS). Note that without a charge on the floating gate the FAMOS acts as a normal n-channel transistor in that when a voltage is applied to the gate, the transistor is turned on. EPROM cells provide a mechanism to hold a programmed state, which is used in PLDs or CPLDs to establish or not establish a connection. To erase the cell remove charge from the floating gate by exposing the device to ultraviolet light. (typical erasure time is about 35 minutes under high-intensity UV light.

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Dr. Ihab Talkhan

- E2PROM, used to create a wired AND-function. It consists of two transistors (select & storage transistors). These transistors are referred to as FLOTOX (Floating gate Tunnel Oxide transistors). It is similar to the FAMOS except that the oxide region over the drain is considerably smaller, less than 10 Ao (Angstroms) compared to 200 Ao for the FAMOS. This allows charges to be accumulated and trapped on the floating gate by a mechanism called Fowler-Nordheim tunneling. E2PROM cells require a select transistor because when the floating gate does not hold a charge, the threshold voltage of the FLOTOX transistor is negative.

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Dr. Ihab Talkhan

- like E2PROM, FLASH cells consist of two transistors (select & storage transistors). They create a wired AND function. The storage Transistor is a FAMOS, so programming is accomplished via hot electron injection. However the floating gate is shared by an eraser transistor that take charge off it via tunneling.

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Dr. Ihab Talkhan

- Random access from any random location.
- It stores information in groups of bits (called “words”.
- A word is a group of 1’s & 0’s (represents numbers, instructions, alphanumeric characters, binary coded information).
- Normally, a word is a multiples of 8 bits (1 byte) in length, where 1 byte = 8 bits.
- Capacity of memory = total number of bytes.

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Communications between memory and environment is done through:

In/Out lines

Address selection lines

Control lines

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n data-in lines

Memory Unit

2k words

n bits/word

K-address

lines

Read

Write

n data-out lines

K-address = specify particular

word chosen

R/W Control = Direction of transfer

- Computer range from 210=1024 words (requiring address of 10-bits) to
- 232 (requiring 32 address bits)

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- Kilo “K” = 210
- Mega “M” = 220
- Gega “G” = 230
- 64 K = 216 (26 x 210 )
- 2 M = 221
- 4 G = 232

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Content of 1024 x 16 Memory L 1K x 16bit

i.e. 10 address lines & 16-bit word

Note: 64K x 10 16 bits in address , 10-bits word

2k = m , m total number of words, K number of address bits (lines)

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- Write
- Transfer binary address of desired word to address lines.
- Transfer data bits that must be stored to data-in lines
- Activate write-in

- Read
- Transfer binary address to address lines.
- Activate read-in

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Select

IN

Out

S

R

R/W

Basic Cell

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Basic

Cell

Select

OUT

IN

R/W = 1read path from F.F to output

0In to F.F.

R/W

m words of n-bits/word consists of n x m binary storage cells

Dr. Ihab Talkhan

RAM

16 x 4

Address- lines

Memory Select

R/W

Data-IN

Data-OUT

Memory Chip Symbol

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- It exhibits three distinct states, two of the states are the logic 1 and logic 0 of conventional logic. The third state is the high-impedance (Hi-Z) state.
- The high-impedance state behaves like an open circuit, i.e. looking back into the logic circuit, we would find that the output appears to be disconnected.

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OUT

IN

ENABLE ) EN)

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- Integrated circuit “RAM” may be either Static or Dynamic

- It consists of internal latches that store the binary information.
- The stored information remain valid as long as power is applied to the RAM

- It stores the binary information in the form of electric charges on capacitors, the capacitors are accessed inside the chip by n-channel MOS transistors.

Dr. Ihab Talkhan

- The stored charge on the capacitors tends to discharge with time, and the capacitors must be periodically recharged by refreshing the DRAM. This is done by cycling through the words every few milliseconds, reading and rewriting them to restore the decaying charge.
- It offers reduced power consumption and larger storage capacity in a single DRAM chip

- SRAM is easier to use and has shorter read/write cycles.
- No refresh is required

Dr. Ihab Talkhan

- Memory units that lose stored information when power is turned-off are said to be Volatile.
- Both SRAM & DRAM are of this category, since the binary cells needs external power to maitain the stored information.
- Magnetic disks, CDs as well as ROM are non-volatile memories, as they retain their stored information after the removal of power.

Dr. Ihab Talkhan

- Combine a number of chips in an array to form the required memory size.
- Capacity = number of words & number of bits/word
- increase in words increase in address
- Usually input and output ports are combined, to reduce the number of pins on the memory package.

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4 x 4 memory

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- It consists of 16 memory cells “MCs”.
- For each memory access, the address decoder decodes the address and selects one of the rows.
- If RWS & CS are both equal to “1” the new content will be written into each cell of the row selected. Note that the output drivers are disabled to allow the new data to be written-in
- If RWS = 0 & CS = 1 the data from the row selected will be passed through the tri-state drivers to the IO pins.

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- Design description
- Synthesis
- Placement
- Routing
- Test Benches for design verification

Design flow diagram

Dr. Ihab Talkhan

- Time-to-market
- Cost
- Design Features
- Performance
- Manufacturing capabilities

Design constraints

Dr. Ihab Talkhan

- Increasing Functionality
- Higher performance
- Lower cost
- Lower power consumption
- Smaller dimensions

· Need to create highly integrated, complex systems with fewer IC devices and less printed-circuit-board PCB area.

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- PCB technology
- Surface mounting Devices (SMD)
- Multi-chip Modules MCMS
- Custom Design
- Application Specific Integrated Circuit ASIC (SC, GA, PLD, CPLD, FPGA)

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- Function description
- Algorithms
- Equation
- Symbols (schematic capture)
- Data from graphs
- Netlist
- Truth table
- Waveforms (timing diagrams)
- VHDL

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Dr. Ihab Talkhan

- It provides a graphical view of the design
- It uses software tools that support schematic hierarchy
- Design modularity ( قابلية التجزؤ )

Dr. Ihab Talkhan

- Control logic must still be generated using traditional design techniques
- Schematic is difficult to maintain
- Schematic capture environment are proprietary ( إمتلاكى ، خاص ), so a designer who works in a schematic capture environment for one project may not be able to reuse material when working on a new project that requires the use of a new schematic capture environment
- The simulation environment supported by PLD schematic capture tool may not fit with the system design environment, making design verification difficult at best.

Dr. Ihab Talkhan

- Electronic Design Automation (EDA) tools
- Accelerated time-to-market schedules

Dr. Ihab Talkhan

- Increase the efficiency of designers
- Facilitate capturing, understanding and maintaining a design
- Not open to interpretation
- Open, not proprietary, standard accepted by industry
- Allow designs to be ported from one EDA environment to another, thus modules can be packaged and reused

VHDL

&

Verilog

Languages satisfy

These requirements

Dr. Ihab Talkhan

- Support complex designs and hierarchy and gate-level to system-level design
- May be used for description, simulation and synthesis of logic circuits
- Support different design entries
- Supports multiple levels of design description

VHDL

&

Verilog

Languages satisfy

These requirements

Dr. Ihab Talkhan

- Semi-custom & Full-custom Application Specific Integrated Circuit ASIC
- High-density Programmable Logic Devices PLDs
- Complex High-density Programmable Logic Devices CPLDs
- Field Programmable Gate Arrays FPGAs
- Hardware Description Language VHDL
- Very High Speed Integrated Circuit VHSIC Hardware Description Language

500 to more than 100,000 gates, thus Boolean equations or gate-level descriptions are no longer efficient to quickly complete a design

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- VHDL ( a product of the VHSIC (Very High Speed Integrated Circuit) program funded by the Department of Defense (US government) in 1970s & 1980s) is well suited for designing with programmable logic devices (it is one language for design & simulation).
- It was endorsed by IEEE in 1986 in its attempt at standardization.
- By December 1987 the IEEE 1076.1 standard for VHDL was approved and a VHDL Language Reference Manual (LRM) was published.

Dr. Ihab Talkhan

- it provides high-level language constructs that enable designers to describe large circuits and bring products to market rapidly.
- It supports the creation of design libraries for reuse in subsequent designs.
- It is a standard language (IEEE standard 1076), thus it provides portability of code between synthesis and simulation tools as well as technology-independent design.

Dr. Ihab Talkhan

- Reduction of a design description to lower-levels (such as netlist), and it serves the needs of designers at any level
- It facilitates converting a design from programmable logic to an ASIC implementation.

Dr. Ihab Talkhan

- Standard
- Government Support
- Industry Support
- Portability
- Modeling Capability (Power & Flexibility)
- Reusability
- Technology & Foundry independence
- Documentation
- New Design methodology

Dr. Ihab Talkhan

- VHDL is an IEEE standard (such as graphic X-windows standard, bus communication interface standard, and so on).
- It reduces confusion and makes interfaces between tools, companies, and products easier.
- Any development to the standard would have better chances of lasting longer and have less chance of becoming obsolete due to incompatibility with others.

Dr. Ihab Talkhan

- VHDL is a result of the VHSIC program, so it is clear that the US government supports the VHDL standard for electronic procurement.

Dr. Ihab Talkhan

- Companies use VHDL tools not only with regard to defense contractors, but also for their commercial designs.

Dr. Ihab Talkhan

- VHDL permits you to simulate the same design description that you synthesized, simulating a several-thousand-gate design description before synthesizing can save a considerable amount of time & effort.
- VHDL is standard, design description can be taken from one simulator to another, one synthesis tool to another, and one platform to another, i.e. VHDL design descriptions can be used in multiple projects.

Dr. Ihab Talkhan

VHDL

CODE

One design

Compiler

A

Compiler

B

Compiler

C

Any Synthesis tool

PCB

Custom

ASIC

Any vendor/device

VHDL provides portability between compilers &

Device independent design

Dr. Ihab Talkhan

- It has powerful language constructs (code description of complex control logic)
- It has multiple levels of design description for controlling design implementation
- It supports design libraries & the creation of reusable components
- It provides for design hierarchies to create modular designs

Dr. Ihab Talkhan

Dr. Ihab Talkhan

- You can create a design without having to first choose a device for implementation, with one design description you can target many device architecture.
- It permits multiple styles of design description, i.e. it permits several classes of design description.

Dr. Ihab Talkhan

U1: xor2 port map(a(0),b(0),x(0)));

U2: xor2 port map(a(1),b(1),x(10);

U3: nor2 port map(x(0),x(1),aeqb);

aeqb (a(0) XOR b(0)) NOR (a(1) XOR b(1));

Netlist

Boolean equationst

aeqb `1` when a = b else `0`;

If a = b then aeqb `1`;

Else aeqb `0`;

End if;

Concurrent statements

Sequential statements

2-bit Comparator

Dr. Ihab Talkhan

- Device-independent design & portability allow you benchmark a design using different architectures and different synthesis tools.

Dr. Ihab Talkhan

- The efficiency the VHDL generates allows your product to hit the market quickly.
- When production volumes reach appropriate levels, VHDL facilitate the development of an ASIC, sometimes the exact code used with the PLD can be used with the ASIC.

Dr. Ihab Talkhan

- VHDL & programmable logic pair facilitate a speady design process, as VHDL permits designs to be described quickly and Programmable logic eliminates NRE expenses and facilitates quick design iterations.
- VHDL & programmable logic combine as a powerful vehicle to bring your products to market in record time.

Dr. Ihab Talkhan

Dr. Ihab Talkhan