EEL 3705 / 3705L Digital Logic Design

1. EEL 3705 / 3705LDigital Logic Design Spring 2007Instructor: Dr. Michael FrankModules #90-99 (Extra Slides): Design Examples Module #91: VGA (Video Graphics Adapter) Color Video Driver Circuit M. Frank, EEL3705 Digital Logic, Fall 2006

2. FLEX 10K: VGA Graphics Programming Examples A Simple VGA Driver, Test PatternGenerator, and Character Generator for the FLEX 10K M. Frank, EEL3705 Digital Logic, Fall 2006

3. Primary Colors in Kindergarten, vs. in Digital Video Pigment color mixing • You may have been taught in kindergarten that red, yellow, andblue are the so-called “primary colors”… • and that all other colors can be produced by mixing these. • This is somewhat true, when it comes to mixing of absorptive pigments (paints); • red, yellow, and blue form a basis for the color space, such that many nice shades can be produced as weighted averages of them, by the mixing of pigments… • But, when it comes to light emission (e.g., from a monitor), the true primary colors are red, green, andblue. • This is because the eye’s three types of cones respond in the most discriminating way to light of these specific wavelengths… • any perceived color can be produced by adding together (not averaging) these colors in different amounts. yellow green orange red blue purple Red light “on” Bluelight on Greenlighton Emissive color mixing M. Frank, EEL3705 Digital Logic, Fall 2006

4. Retinal cone response curves& typical emissive RGB basis wavelengths video green(~550 nm) video red(~700 nm) video blue(~450 nm) M. Frank, EEL3705 Digital Logic, Fall 2006

5. A simple, generic variant of the oldPC Video Graphics Adapter (VGA) standard • Colors: 8 • 3 bits, with 1 bit each for red, green, blue • 000 = black, 001= blue, 010 = green, 011 = blue + green = cyan, 100 = red, 101= red + blue = magenta, 110 = red + green = yellow, 111 = red + green + blue = white • Display resolution: • 640 pixels/row (horiz.) × 480 scan lines (vert.) • Display update frequency: • Usually ~30-60 Hz M. Frank, EEL3705 Digital Logic, Fall 2006

6. VGA Cable Pinouts (p.13) M. Frank, EEL3705 Digital Logic, Fall 2006

7. Video Scan Line Timing • fclk = 25.175 MHz; tclk = 39.722 ns (p. 26) 782tclk 142tclk 95tclk 806tclk 640tclk= 25.42 µs = 48tclk = 95tclk 32.02 µs = 806 tclk = 24tclk M. Frank, EEL3705 Digital Logic, Fall 2006

8. Scan Line Timing Hardware M. Frank, EEL3705 Digital Logic, Fall 2006

9. Video Frame Timing • trow = 32.022 µs 514 rows (p. 27) 34 rows 11 rows 32 rows 2 rows 525 rows 16.8 ms 15.37 ms M. Frank, EEL3705 Digital Logic, Fall 2006

10. Frame Timing Hardware M. Frank, EEL3705 Digital Logic, Fall 2006

11. Entire VGA Driver Schematic M. Frank, EEL3705 Digital Logic, Fall 2006

12. Example Test Circuit for VGA Driver • Goal: Generate diagonal color test pattern • Computed by formula: RGB2..0 = (row + col)6..4 M. Frank, EEL3705 Digital Logic, Fall 2006

13. Photo of VGA CRT Monitor Screen Circuit works perfectly! Files are in VGA_example.zip on BB M. Frank, EEL3705 Digital Logic, Fall 2006

14. Circuit to Demonstrate RGB Color Mixing • Project archive file: • VGA_RGB_demo_v2.zip • Under control of the first 3 DIP switches, • Display a solid red rectangle filling the right half of the screen; • display a solid green rectangle filling the bottom half of the screen; • display a solid blue rectangle filling the middle ¼ of the screen. • When multiple of these rectangles are turned “on” simultaneously, • in the regions where they overlap, • you can see the apparent colors that are produced by the various combinations of red, green, and blue light • Each filled rectangle is generated by appropriate comparators acting on the x and/or y screen coordinates • x≥ 320 • Is true on the right half of the screen • y≥ 240 • Is true on the bottom half of the screen • (160 ≤ x < 480) & (120 ≤ y < 360) • Is true in the middle ¼ of the screen. Red rectangle Green rectangle Pushbuttoninputs Bluerectanglesubcircuit M. Frank, EEL3705 Digital Logic, Fall 2006

15. Output of VGA_RGB_demo • Here is what the display looks like when DIP switches 1,2,3 are all “up” M. Frank, EEL3705 Digital Logic, Fall 2006